Blog Review: Sept. 16

Siemens’ Harry Foster finds that first-silicon success has fallen sharply, with only 5% of IC/ASIC respondents to the latest functional verification study reporting first-silicon success in 2026, compared with 14.4% in 2024.

Synopsys’ Thomas Andersen argues that as chip development faces an engineering capacity crunch, implementing AI across the entire flow becomes necessary to sustain the pace of innovation.

Cadence’s P. Saisrinivas introduces how to calculate minimum clock time period using concepts such as on-chip variation and common path pessimism removal to ensure a chip operates reliably in the real world.

Arm’s Ash Naik shows how to use ExecuTorch to partition and optimize one PyTorch model across CPUs, GPUs, and NPUs using five target-specific execution paths.

Keysight’s Sameer Dixit warns that AI systems introduce entirely new classes of security risks to enterprise environments, driving the need for a comprehensive AI security assessment framework.

SEMI’s Mayura Padmanabhan and Nishita Rao chat with Erik Hosler of OBSIDIA Semiconductors about counterfeit electronics, traceability, trusted hardware, AI infrastructure, and the role industry collaboration can play in securing the semiconductor ecosystem.

Plus, check out the blogs featured in the latest Test, Measurement & Analytics and Low Power-High Performance newsletters:

Onto Innovation’s Huayuan Li, Alex Hong, Johnny Mu, and Timothy Kryman show how to improve visibility into deposition variation.

Synopsys’ Guy Cortez, Dan Alexandrescu, and Aaron Barker explain how to align production measurements with device behavior and pre-silicon expectations.

Teradyne’s Melvin Lee illustrates why passing ATE no longer guarantees success in the field.

Advantest’s Don Ong sits down with ISIG’s Salah Nasri to discuss the impact of supply chain interdependencies and strategic alliances.

PDF Solutions’ Christophe Begue looks at the disparity between how much data is generated during chip manufacturing and what gets analyzed.

Nordson’s YiPeng Zhou finds that bond testing is emerging as a critical control point for long-term performance and yield.

proteanTecs’ Nir Sever explains why it’s critical to monitor every chiplet inside a system-in-package.

Rambus’ Phillip Swart looks at building configurable PCIe subsystems that span local expansion, shared resource domains, and longer-reach topologies.

Cadence’s Nagendra Varma outlines the benefits of transforming established SoC design paradigms into system-level fabrics capable of supporting next-gen AI, HPC, and data center workloads.

Arm’s Jeevan Bhoot demonstrates a method for combining a novel weight format with quantization-aware training to reduce model size while retaining accuracy for multimodal AI.

Synopsys’ Madhumita Sanyal examines the implementation of 64.0 GT/s PCIe connectivity in a stacked-die, face-to-face 3D architecture.

Quadric’s Steve Roddy digs into the advantages of a single, software-controlled core that handles matrix, vector, and scalar code in one execution pipeline.

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