Validating PCIe 6.0 Connectivity In A 3D Multi-Die Test Chip

AI, high-performance computing (HPC), data center switching, and storage systems are increasing the amount of data that must move across interfaces and between heterogeneous dies, or chiplets. That demand is exposing limits in traditional monolithic system-on-chip (SoC) architectures. Synopsys’ 3D PCIe 6.0 test-chip demonstration shows that 64.0 GT/s PCIe connectivity, with up to 128.0 GB/s delivered through an 8-lane configuration using PAM4 signaling, can be implemented and validated in a stacked-die, face-to-face 3D architecture rather than only in a conventional 2D design.

Linear transmitter eyes and receiver eyes at 64 GT/s exceeding PCIe 6.0 BER requirements by multiple orders of magnitude.

3D PCIe 6.0 test-chip demonstration

3D multi-die design offers a path to higher bandwidth, tighter coupling, and improved efficiency by reducing interconnect distance between dies. In 2.5D packaging, dies are placed side by side and connected through interposers; in 3D packaging, dies are stacked vertically to shorten interconnect distance and enable tighter coupling between heterogeneous functions.

The test chip for the 5-nm PCIe 6.0 PHY, with design updates for 3D-IC technology, is built on an existing PCIe 6.0 test-chip implementation. The excellent silicon results confirm that high-speed PCIe 6.0 IP can be adapted, packaged, brought up, and measured in a 3D environment, an increasingly necessary requirement as customers move from monolithic SoCs to multi-die designs. This enables homogeneous and heterogeneous die integration for high performance, high compute density, energy efficiency, low latency, higher integration, smaller form factors, better power and signal integrity, and lower power consumption compared with current state-of-the-art packaging approaches. The achievement is not just the PCIe 6.0 eye or loopback result in isolation, but the connection between 64 GT/s PCIe behavior, 3D packaging, validation infrastructure, and customer system requirements for AI, HPC, data center switching, and storage. Synopsys’ PCIe 6.0 at 64 GT/s, along with 3D-ready implementation expertise, helps customers design AI accelerators, HPC processors, data center switches, SmartNICs, DPUs, SSD controllers, and CXL-enabled systems with compact form factor.

PCIe 6.0 implementation challenges in 3D packaging

This 3D implementation introduced several challenges, including 3D PHY architectural analysis, TSV implementation and dummy die strategies to optimize performance, accurate modeling of interactions between the top and bottom dies, full-stack modeling and verification of inductor implementation, and minimizing added TSVs while meeting PCIe 6.0 performance goals.

This milestone reinforces Synopsys’ long PCIe legacy, including more than two decades of expertise, silicon-proven PHYs, digital controllers, IDE security IP, verification IP, and extensive third-party interoperability testing, covering hundreds of PCIe 6.x implementations and approximately 4,000 customer tape-outs across seven generations of PCI Express. The results demonstrate a path from standards leadership to mature PCIe IP, 3D-aware implementation, and silicon success. They also connect the proven PCIe ecosystem with emerging multi-die design architectures and give customers designing the next generation of AI infrastructure, HPC platforms, storage systems, and data center fabrics a clearer path for high-performance connectivity into 3D packaging without sacrificing the validation discipline, interoperability experience, and IP completeness that modern systems require.

As a trusted partner, Synopsys is driving the industry’s transformation to multi-die designs with a comprehensive and scalable solution for fast heterogeneous integration. The solution, including EDA and IP products, enables early architecture exploration, rapid software development and system validation, efficient multi-die/advanced package co-design and optimization with multi-physics analysis, robust die-to-die and chip-to-chip connectivity, and improved manufacturing and reliability.

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