AMBA Over UCIe: Building Coherent Multi-Die Systems
As computing systems evolve to meet the demands of AI, data centers, and high-performance workloads, the challenge is no longer just about building powerful IP blocks. It is about connecting them efficiently at scale.
The transition from monolithic SoCs to chiplet-based architecture has unlocked new possibilities in modularity and scalability. However, it has also introduced a critical requirement: A high-performance, standardized interconnect that can extend proven on-chip protocols across multiple dies.
This is where UCIe plays a transformative role. Rather than replacing existing protocol ecosystems, UCIe enables them to scale beyond the boundaries of a single die, bringing mature standards like AMBA into the chiplet era.
The evolution of AMBA in a chiplet-driven world
AMBA protocols such as AXI and CHI have long been the backbone of modern SoCs. AMBA CHI provides a robust framework for cache-coherent communication between processors, accelerators, and memory subsystems within a chip.
However, these protocols were originally designed with a key assumption that all communication occurs within a single piece of silicon. As systems move to multi-die architecture, this assumption no longer holds.
To address this, AMBA introduced CHI Chip-to-Chip (C2C), an extension of the CHI protocol that enables coherent communication across dies. CHI C2C preserves the semantics and efficiency of on-chip CHI while adapting it for chiplet-based systems. But while CHI C2C defines how coherent messages are structured and managed, it still relies on a transport mechanism to move these messages efficiently between dies.
UCIe: The foundation for scalable interconnect
UCIe provides the foundational transport layer that transforms CHI C2C from a protocol extension into a scalable system-level solution.
Designed as a standardized die-to-die interconnect, UCIe offers:
- High bandwidth and low latency communication
- A layered architecture (protocol, adapter, PHY)
- Support for multiple protocols, including PCIe, CXL, streaming, and custom protocols
This flexibility makes UCIe an ideal transport for extending AMBA protocols across chiplets.
UCIe does not redefine protocols like CHI. It enables them to operate seamlessly in multi-die environments.
How UCIe features enhance CHI C2C performance in multi-die systems
While CHI C2C defines the coherency model and message structure across chiplets, the efficiency and scalability of such systems depend heavily on the underlying transport.
This is where UCIe plays a critical role not just as a carrier, but as an enabler that enhances the effectiveness of CHI C2C in real deployments.
Verification challenges in CHI C2C over UCIe
As UCIe scales AMBA protocols across chiplets, verification must evolve to handle cross-layer interactions, coherency correctness, and system-level complexity.
Summary
At its core, UCIe enables a fundamental shift from tightly coupled, single-die systems to scalable, coherent multi-die architectures. By extending AMBA protocols like CHI beyond their original boundaries, UCIe transforms established SoC design paradigms into system-level fabrics capable of supporting next-generation AI, HPC, and data center workloads.
While CHI C2C brings coherence and protocol intelligence to multi-die architectures, it is UCIe that enables these capabilities to scale efficiently in real hardware.
UCIe does not just transport CHI traffic. It enhances its performance, reliability, and scalability across chiplet-based systems.
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