Scaling Thermal Analysis From Transistors To Data Centers
Key Takeaways:
- Thermal is becoming an architectural constraint, requiring trade-offs in power, performance, reliability, floor-planning, packaging, and cooling.
- Chiplets and advanced packaging make thermal analysis harder because hotspots, crosstalk, materials, and cooling must be evaluated across the entire package and system, not just individual dies.
- More scalable multi-physics modeling, reduced-order models, digital twins, and tightly coupled physics solvers are needed to accurately predict thermal behavior.
Experts at the Table: Semiconductor Engineering sat down to discuss thermal management and heat-related trade-offs in chip and system design with Lang Lin, director of product management at Synopsys; Jack Berg, vice president of business development at Silvaco; Satish Radhakrishnan, head of semiconductor and electronics at Vinci; Chris Mueth, director of new markets management at Keysight EDA; and John Ferguson, senior director of product management at Siemens EDA. What follows are excerpts of that conversation, which was held behind closed doors at the recent Design Automation Conference.
L-R: Silvaco’s Berg; Synopsys’ Lin; Vinci’s Radhakrishnan; Keysight’s Mueth; Siemens’ Ferguson.
SE: What are the big trade-offs in data centers that are required to keep racks of servers from overheating?
Berg: There are trade-offs at the chip level, particularly dynamically, at the package level, and across the entire system. It’s extremely important to get the thermals correct, and as you package that in a multi-die package, to abstract that. But you don’t want to abstract it so far that you lose fidelity in both static and dynamic thermal processing.
Lin: Design for thermal involves trading off multi-physics factors, such as your power budget, floor plan, routing resources, and your timing budget — any of which can affect signal integrity and warpage. Temperature plays a role in all of these things. It can change your delay, timing, and power. You have to prioritize thermal for design optimization. Then, does that affect other factors? Can you tape out a chip by fulfilling all the requirements involving different types of physics? You have to make those trade-offs and choose the best options.
Mueth: For multi-physics, the big three are performance, mechanical, and thermal. Classically, those are traded off against each other. But you also need to include reliability. For high-reliability applications, the trade-offs are package size, performance, and reliability. Those are what you need to optimize when you’re doing floor-planning.
Radhakrishnan: Thermal has shifted more toward an architectural discussion. It used to be more about transistor density and how much you can pack in. Now, from an architecture perspective, you have to think about thermal. How am I going to package it? How am I going to move the heat away? How much heat density can I put into a chip? That’s becoming a primary focus. But it’s more than transistors. How much heat can I tolerate with vertical integration, and what kind of cooling can I do?
Ferguson: We’re all basically on the same page here. It’s about how we get there. It’s about the performance of tools, the performance of the chips, and reliability. Our focus right now is going from the chip to the package to the board and to the system — all the way to the data center or other systems. The problems are similar, but the challenges get bigger. These are much bigger systems in many cases. They take a lot more power and generate a lot more heat, and so we’ve got to do more than what we’re doing just at the chip level to bring that heat down. What we do at the chip level is incredibly important, though, because that’s where the heat is being generated.
SE: So where do you start? There’s insatiable demand for performance, which is what’s causing the thermal problems. At the same time, the benefits of scaling alone are diminishing, so we are now packing more compute power into a multi-die assembly. That creates other thermal issues.
Radhakrishnan: For packaging, we’re seeing materials innovation with TIM 1 and TIM 2 [layers in thermal interface materials]. That’s ongoing, where people are trying to break the barriers. That’s one change. The second part is the cooling itself, with things like cold plate or immersion cooling. There’s also direct chip cooling. Instead of cooling the lid, the cooling is moved directly onto the chip. Immersive cooling and two-phase cooling are different architectures that you’ll be seeing in the industry this year and next year.
SE: Is that just for a single chip?
Radhakrishnan: It’s for the entire package. You need liquid cooling, plus you need to take the heat away.
Lin: You also need more accuracy and higher fidelity for the temperature. Cooling is about taking the heat away, but you also need to know where the heat is. You have to predict that, which means you have to do thermal simulation down to the device level. In the past, we were doing PVT corners. You have high, low, and medium temperatures. Three corners and you’re done, and then you move forward. Everybody is looking for the temperature of a specific transistor. ‘Tell me the region where the hotspot is. Give me that number.’ The tools should be able to help predict exactly where those hotspots are and start to do the design changes. We have done that for voltage. IR drop is now in good shape, and we’re getting per-gate drop. But we haven’t done per-gate thermal.
Berg: Depending on how the software is developed, the hotspots can change. It’s not a straight hardware problem. At the chip level, you may have 20 or 25 different chiplets. Understanding what’s happening inside the package is essential because both of those become constrained, and both need to have the fidelity necessary to ensure reliability. Typically, the first thing that happens when you don’t look at heat closely enough is you get electromigration. You get different phases occurring in materials, and that creates a reliability problem.
Mueth: It all comes down to multi-physics. We tend to think of multi-physics as heat, power, and stress, but it’s much more than that. There are a lot of different physics that are impacting each other — all types of noise and other issues. They all have to be known, and we need to be able to bring it all together to get accurate results, and we need to get them early and fast. This is where the agentic MCP (Model Context Protocol) approach is coming in, and that brings its own issues. AI is not perfect. It’s no more perfect than humans, and it can make mistakes just like humans. But it’s hard for a human to go back into a decision AI has made and figure out what mistakes it made.
SE: Part of the solution is orchestration, right? We’ve got vapor caps, liquid cooling, and direct cooling, but it also depends on where you process data. Is it happening just in one place, or is it scattered across different chiplets?
Mueth: That’s an interesting problem from a design perspective, because we can’t have one person design the whole thing. It’s impossible. So you’ve got people who care about a given chip, and that’s the detailed information they need for that chip. You have other people who care about the package or beyond, and maybe they don’t need as much fidelity as the people developing the chip. You need capabilities that provide the level of detail needed by the person driving a specific task.
Lin: To deal with a whole system and get accurate temperatures everywhere is computationally very hard. But I’m seeing a trend toward building some foundation model for a particular block or chiplet to provide a simplified thermal behavior of those structures. So when you do simulation, you probably create a foundational model that can reduce some computation cost, or pre-compute with the model plugged in. Then you can focus on some critical error and do an accurate simulation. That’s one solution. So you combine some fast, less-accurate model with a slow foundational model.
Radhakrishnan: The ASIC chips are getting so hot that HBM is going to custom HBM. They’re trying to move some power from the ASIC to the custom part, but now you have to evaluate where the crosstalk is going because the ASIC is going to be hotter, and the HBM is going to be hotter. You need to be able to handle everything. So with chiplets, people are splitting up functions in terms of power, and they are looking at co-packaged optics to bring the networking closer. You need to be able to handle crosstalk, understand how everything is going to heat up, and you need to evaluate performance individually and together as a system.
Mueth: There are some techniques you can use, like superposition or reduced-order modeling, to help scale. But you need to tackle this at the architecture level so that when you do your layouts and floor planning and finish the design, and then go back and do verification at the end, you have some reasonable confidence that you’re not going to have to re-spin the design.
Berg: Starting at the chip level and working up, you need mechanical, thermal, and electrical physics solvers to do that. They need to be congruent with one another and have a simple solution at this point that’s consistent with all of them. That’s pretty hard to do, and coming back to the MCP, that’s absolutely necessary — not necessarily sufficient, but absolutely necessary. To get architects to actually build something that’s reasonably close, there has to be a digital twin or surrogate model level that allows the architect to make those trade-offs at the chip level. Now, just because it’s working at the chip level, there also needs to be a surrogate model at the package level, as well. That involves what is essentially a digital twin based on how you’re doing the packaging, and all of that goes back to physics solvers and getting them to be consistent with one another. That’s always a nasty issue, because we’re talking about different physics solvers with different partial differential equations that are cross-coupled to each other. That’s a bit difficult. But abstracting that to a digital twin or surrogate model, both at the chip level and at the package level, and even at the system level, is very critical. Obviously, there are trade-offs with respect to TIM 1 and TIM 2, as well as other materials, and what the cooling at the system level needs to be in order to do this. But those trade-offs can be made as you look at the entire stack at this point.
Mueth: There are three types of physics solvers out there. There’s the decoupled method where you’re pushing one physics into another. And then you have a loosely coupled solver, which is iterative. So you have enough coupling where you have to take into account the impact of one physics type on another, but you do that iteratively. And then there is the direct-coupled physics solver. What you see out there are direct-coupled physics solvers that do stress and thermal at the same time. Those are out there today, and that’s what you need for a lot of the manufacturing problems when you’re trying to look at chiplet packages and thermal compression bonding. You need direct-coupled solvers for those kinds of problems.
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