Hardware Assisted Verification Is Key to AI Chip Design

By JUERGEN JAEGER, Director of Prototyping Product Strategy, Siemens EDA

A decade ago, only the largest chipmakers could justify investing in hardware emulation to verify their biggest SoC designs. Juergen Jaeger of Siemens EDA explains why hardware-assisted verification — emulation, enterprise prototyping, and FPGA prototyping — has since become a must-have across mainstream IC design, driven largely by the scale and software-defined complexity of AI chips, where the software increasingly dictates what the hardware needs to do before a single transistor is taped out.

The article breaks down how the three HAV technologies fit together: logic emulation validates RTL-level IC and mixed-signal blocks before they’re integrated; enterprise prototyping runs three to five times faster to give whole design teams earlier insight into hardware/software interaction; and FPGA prototyping lets software developers start building middleware and applications on real silicon-equivalent hardware well before tape-out. Jaeger points to Siemens EDA’s Veloce CS platform as an example of unifying these previously siloed systems under a common operating environment and compiler, so errors surface faster and are easier to trace between systems.

Two trends stand out for where HAV is headed next: comprehensive digital twins that extend emulation beyond logic verification into thermal and power behavior for mission-critical systems, and cloud-based emulation that lets startups and small design teams lease time on emulation and prototyping systems rather than buying and housing the custom racks themselves — effectively democratizing a verification capability that was, until recently, available only to the largest chipmakers.

Click here to read the full article in Semiconductor Digest magazine.

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