Redefining Processes At Sub-2nm
Key Takeaways:
- Sub-2nm manufacturing is blurring traditional process boundaries as shrinking dimensions and tighter margins make test, metrology, inspection, and manufacturing increasingly interdependent.
- More sensitivity creates more noise. Advanced inspection can detect millions of potential defects, making it harder to distinguish harmless process variation from issues that affect yield, reliability, or performance.
- Data needs to flow back and forth across a chip’s entire lifecycle so it can be acted upon as needed.
The lines between discrete semiconductor manufacturing processes are starting to blur at sub-2nm nodes as transistors continue to shrink, sensitivity to various processes rises, and the amount of margin available to minimize problems disappears.
At these dimensions, a single atom can change how a chip behaves, and even a gentle wafer probe can damage an oxide layer or a via on a thinned substrate. Process variation can cause false error reporting in metrology. And a nano-sized particle that remains on a chip after removing a sacrificial material can turn an expensive multi-die stack into scrap.
“People are going from trying to probe chiplets to having sacrificial pads because they don’t want to damage the bumps that we’re actually going to bond to,” said Lee Harrison, director of automotive IC solutions at Siemens EDA. “And now we’re seeing hybrid bonding, which is a super cool technology, but there’s no way you’re going to be able to probe a hybrid bond and keep it in one piece. We’re seeing some customers doing wafer bonding before test because you’re getting these extra-thin dies and extra-thin wafers.”
At older nodes, there was enough margin built into manufacturing processes to ignore these kinds of issues. Substrates were thicker, less prone to warpage, and structures were more stable. But below 2nm, many of these dies are collections of chiplets, because demand for processing far exceeds the number of transistors that can be packed into a reticle-sized die. That increases thermal density, elevates structural stress, and generates a huge number of unknowns because different workloads can stress chips in different ways. At the same time, increasing the overall performance of a device requires everything to be smaller, thinner, and subsequently more fragile, creating a confusing array of overlapping and often contradictory needs.
Large AI data centers are fully aware of these issues, which is why they are migrating toward redundant server clusters. “You’re probably going to have some manufacturing problems, so we’re building solutions for redundancy,” said Rob Kruger, product management director for multi-die strategy and 3D IP at Synopsys. “So you can have redundant clusters instead of redundant lanes and a 3D interconnect, because if you have a fault — it might take out a whole slew of faults, not just one — and then you have multi-die tests, you have to test these dies before you integrate and then after integration. There are some standards there, which are helping, and having hierarchical test servers on each die is becoming common. You can test before you package, after package, and then have capabilities to repair packages if there are problems using redundancy. They can do that for UCIe and for 3D connections.”
That effectively moves margin outside the individual dies within a package, enabling hot swapping of compute resources. Ironically, this approach originally was developed for mainframes and minicomputers several decades ago to reduce downtime, but it was largely abandoned in the 1990s with the introduction of inexpensive servers running Windows NT and various flavors of Unix.
False positives
Shrinking features enabled the proliferation of cheap hardware, but the laws of physics are starting to reverse those cost benefits. Deploying exactly the same processes across a wafer can produce different results in different sectors of that wafer. And while this variation in processes is generally predictable, it can impact other processes that in the past were not affected.
“We are seeing an explosion in the number of defects detected on the wafer to millions of defects,” said Prasad Bachiraju, senior director of business development at Onto Innovation. “Because of the tool sensitivity, when you’re trying to capture the critical defect, it is actually capturing the neighborhood and the process variation also as a defect. That’s all noise and nuisance.”
Others agree. “What we are seeing is that advanced nodes are making the industry less able to rely on inspection signals alone to decide what matters electrically,” said Noam Brousard, vice president of solutions engineering at proteanTecs. “At 2nm and below, the volume of potential indications can be enormous, and many signals may reflect local process variation rather than a defect that will become a functional or reliability problem.”
There is no single solution for this. Instead, multiple approaches are required to work in sync, under continuous monitoring, and each needs to be evaluated and implemented in the context of potential interactions with other solutions.
“One of the paradigm changes in how we monitor quality and health is that we are not tracking a single indicator, but a collection of many data points,” Brousard said. “Individual indicators, such as process variation, temperature, or voltage, may suggest an out-of-bounds condition, but they can also reflect normal variation rather than a true defect. As designs become more complex, there are more clues that may point to a defective part, but it is increasingly difficult to distinguish between harmless variation and a condition that will affect operation. You need to look at the end result — how the actual logic is being affected by the combination of many possible factors.”
In addition, there are more insertion points that can cause defects, and there is more data being produced than can be classified and processed using traditional cloud-based methods. The best way to comprehend that data is by abstracting it.
“The industry has shifted to virtual capabilities, and away from iterative work, to do R&D,” said David Fried, chief AI officer and corporate vice president for Semiverse Solutions at Lam Research. “A lot of virtualization, modeling, and optimization has happened, so I have high hopes that the types of structures and technologies that are marching toward manufacturing in these nodes are designed in a more robust way than technologies of the past. Hopefully what that translates to is that we don’t have late showstopper-type problems in these technologies. It’s a challenge to ramp these technologies. The individual process variabilities are still going to be really challenging. Hundreds of processes have to come together, and you need to account for variations in all those processes. Historically, this has been done by just running scads of hardware through the fab and trying to use data measurement, metrology, and inspection to map out the boundaries of all these variations. But there is an amazing amount of process complexity. There are so many steps in the process that you just can’t map out the full space with hardware anymore.”
Looking deeper, wider, and more often
There are no real surprises here. What’s changed is the sheer volume of things that need to be considered.
“Warpage is pretty well understood,” said Juliette Vandermeer, product marketing manager at Bruker Semiconductor. “You know the process, you know what kind of silicon film you grow on the wafers, and you know, ‘Okay, this will warp that way.’ But if something gets really warped, it also has microfractures.”
Finding those fractures requires looking much deeper into the various metal layers, often using X-ray diffraction imaging — also called X-ray tomography — to see and measure what’s actually happening inside a chip or package at each process stage or insertion point.
“The layers are getting thinner, so a higher precision is required,” Vandermeer said. “The challenge is really the thickness and the concentration, which is the growth process. There is temperature control during the growth, and interfacial roughness has an impact on the quality of the resistor channels. These are parameters we measure, and if there is an error at the front end, that can propagate to the very end. Our customers need to be certain that a process is well controlled. The process specs need to be tight, in the angstrom range, and our metrology specs need to be in the sub-angstrom range.”
Fig. 1: X-ray diffraction imaging can find defects in wafers that can cause catastrophic structural failure before breakage occurs. Source: Bruker
This is more than just the overlapping of process steps during manufacturing. It’s a compression of the whole design-through-manufacturing chain, and beyond that into the field. Data needs to flow in multiple directions and be analyzed outside of traditional silos, and extracting that data requires more types of testing, inspection, and metrology equipment, as well as infrastructure to sort through all of it and take action in real-time.
“We’re starting to see a mixture,” said Siemens’ Harrison. “The regular ATPG scan is still very dominant in the whole test strategy. You might have a couple thousand processing elements, so you would test your processing elements with ATPG. But if you’re doing some kind of core harvesting, then you might pick up another strategy, whether that’s BiST (built-in self-test) or some other kind of functional test, to do the reallocation of lanes or interconnect and things like that. And then, testing in the field is becoming a significant demand right now. I scoped out our original in-system deterministic test product back in 2019, where we had a couple of automotive customers asking us for better test quality than logic BiST. However, what’s happened is the guys doing the data centers have really taken hold of that technology, and they’re driving it forward using the kind of periodic testing they do on data centers to make sure everything is still working. They’re doing it to save a huge amount of cash in terms of being able to understand when to do that preventive maintenance instead of just guessing at it.”
Just setting limits on temperature or tracking the speed of data movement is no longer sufficient. What’s required is a hierarchical way to coordinate, interpret, and prioritize data at every phase of manufacturing and operation, and then determine where it will best be used.
“Margin Agents allow us to answer a more important question than temperature alone can answer,” said proteanTecs’ Brousard. “They tell us how safe a specific buried domain actually is, not just how hot it is. That distinction matters significantly in a stacked structure. In a shingled or vertical stack, thermal coupling between layers can degrade the effective timing margin of a domain even when nothing inside that domain has changed. A neighboring tier may run hot; self-heating may increase the local temperature, and timing paths in the domain above or below it may lose margin as a result. A thermal sensor can tell you that temperature increased, but it cannot tell you whether that increase created an actual timing risk. The relationship between local heat and margin loss depends on which paths are affected, how they are routed relative to the hot layer, and what voltage they are running at.”
That might affect only a single die on a wafer, or it could affect an entire panel or advanced package.
“When a wafer is tested at the foundry, they don’t know where those chips are going to go to be packaged, assembled, and tested,” said John Kibarian, CEO of PDF Solutions. “They’ve got to know where to go to send the material to take the human out of the loop. That’s really not something that’s gone on. We call that the orchestration layer. This is like a low-code or no-code way of connecting your apps. If you think about PLM, ERP, and MES systems, your engineering data, manufacturing yield data, and ultimately your design automation information, you need to be able to get that information in order to take the human out of the loop so AI can make appropriate decisions.”
Conclusion
The smaller the features on a die, or the denser the package, the bigger the challenge in keeping track of everything. At each new node below 2nm, more testing, more precision, and more information about what’s going on at the surface and within a chip or package are all essential. But in addition to that, each process needs to include cross-over data and a level of awareness about what impact each step can have on other process steps, and what used to be defined spaces for testing, measuring, and inspecting are now a collection of overlapping combinations of steps that must be considered both individually and collectively.
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