Arteris, Arm Partner to Strengthen Hardware Security Verification

Arteris Inc. has expanded its long-standing collaboration with Arm to broaden the use of the Cycuity Radix hardware security assurance platform across future processor development programs. Building on several years of cooperation, the agreement extends the adoption of security verification technologies designed to identify hardware vulnerabilities during the design phase rather than after silicon implementation.

As processor architectures become increasingly complex, hardware security has emerged as a critical aspect of semiconductor development. Modern CPUs must address a growing range of attack vectors while maintaining performance and power efficiency, making early security verification an essential element of the design process. The expanded partnership reflects this shift by embedding security analysis directly into Arm's processor development workflow.

Cycuity Radix is used to analyze relationships between hardware assets, privilege domains, and potential attack paths within a processor architecture. By providing visibility into security-relevant interactions and identifying possible attack surfaces, the platform enables engineering teams to detect design weaknesses before fabrication, reducing the need for costly post-silicon mitigation measures.

Rather than treating security verification as a final validation step, Arm incorporates the technology throughout CPU development. The process begins with architectural and microarchitectural security risk assessments that identify critical assets and evaluate them against established threat models. These analyses are then translated into security objectives that can be verified continuously as the processor design evolves.

Automation is a key aspect of the methodology. Cycuity Radix allows security properties developed for one processor design to be reused across multiple CPU families, improving verification efficiency while maintaining consistency between successive product generations. This scalable approach enables engineering teams to evaluate increasingly complex processor architectures without significantly increasing verification effort.

By identifying potential vulnerabilities earlier in the development cycle, the methodology reduces design risk and allows security issues to be corrected before manufacturing. Integrating security verification into the design flow also shortens the feedback loop between architecture, implementation, and validation, contributing to more robust processor designs.

The expanded collaboration highlights the semiconductor industry's growing emphasis on hardware-level cybersecurity.

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