The Evolution in Data Center Power Distribution PCIM Panel, Part 4: DC/DC platforms and VPD

Part 1 of this series covered the key takeaways from Power Electronics News’s panel discussion at PCIM Europe 2026 on the 800 V DC transition. Part 2 turned to the solid-state transformer, examining the commercial case, the device technology debate, and where the SST sits in the power chain. Part 3 covered rack-level energy storage—battery backup units (BBUs) and capacitor bank units (CBUs)—and data center protection, with a focus on solid-state circuit breakers (SSCBs). This final part will discuss the remainder of the panel with the DC/DC platforms and vertical power delivery (VPD) aspects of data center power.

*Panelists for the PCIM 2026 panel discussion: “The Evolution in Data Center Power Distribution Panel.” (Source: Power Electronics News)*

DC/DC platforms

The discussion shifted towards DC/DC platforms, where many power semiconductor vendors, including the panelists, released reference designs ranging from 800-to-48V, 800-to-12V, and 800-to-6V. The first question asked whether this design would coexist indefinitely.

Di Franco offered a good glance at the thought process behind these power delivery boards (PDBs): “This 800V DC architecture evolution is a multi-step process. So clearly, at the beginning, you need to ensure compatibility with the existing infrastructure. This means that you need a sidecar—you are ensuring compatibility with the AC distribution down to 800 V or ±400 V, and, on the other side, with the 800-to-48V, you ensure compatibility with the 48-volt bus standard at rack level. However, this is still a transition step.”

Vaughan-Edmunds shared where Navitas was currently seeing customers land: “What we’ve seen with customers now is they want to go straight from 800 V to 6 V, which eliminates the IBC stage, improves the system efficiency, and also frees some of the real estate on the board. So we see that being a trend now. We see some more conservative customers who want to do 800-to-48V, and we see some aggressive customers who want to go straight from 800-to-6V.”

The panelists agreed that 800V-to-48 V DC/DC platforms were necessary to support the new sidecar rack rollouts, but there was more gray area around whether stepping down to 12V or 6V was the solution. Deboy described the clear benefits of moving down to 6 V: “The VRM stage takes a clear benefit if it operates from 6 V versus 12 V. You are cutting switching losses by a factor of four, because the switching loss scales with the square of the voltage. If you can use lower-voltage technology nodes at 15 V instead of 25 V, that gives you another 0.5% efficiency gain. So the 6 V for the GPU is kind of settled.”

Deboy also explained how the board architecture itself determines which path operators take: “If customers take a mezzanine card approach, where the GPU is on a separate board, 800-to-50 V is a good option, because then it goes 50 V up to the mezzanine card [via the backplane], and you place the IBC on the mezzanine card—and that’s for repairability and maintenance. If the customer goes for full board optimization and puts everything on the motherboard, they go 800-to-6 V directly.”

Scalia offered a practical perspective on what the minimum number of conversion stages could realistically look like. While 6 V is attractive as an intermediate bus, enabling lower-voltage transistor nodes in the VRM and cutting switching losses, it introduces its own challenges: “6 V is fantastic, because it’s a lower node, but the problem is capacitance and bandwidth. So we need to reach a reasonable number of converters. This means that 6 V will definitely do the job, and then it’s about achieving efficiency—96%+—because, in the end, there are other solutions: we can probably do 98.5% or 98.7% in the first stage, and then we can have a very good second stage. It’s a question of getting the best performance, efficiency, and cost of this solution.”

Scalia’s point is that despite the capacitance and bandwidth challenges that 6 V introduces at the VRM input, the efficiency targets are achievable—with the bus converter stage hitting 98.5-98.7% and the downstream VRM stage able to deliver strong performance as the technology matures.

On the question of which voltage architecture operators actually choose, Scalia was clear that there is no universal answer: “It’s a PDB strategy. There is no one-size-fits-all solution because implementations differ. Some OEMs may already be going directly to 6 V, while others design their PDB in a way that keeps 48V in the chain.” The choice, as both Scalia and Deboy noted, ultimately comes down to whether the OEM puts the IBC on a mezzanine card or integrates everything directly onto the motherboard.

While Deboy seemed to settle in on the move to 6 V, cutting VRM losses by 4x and enabling lower-voltage nodes, Di Franco cautioned that the closer conversion got to the GPU, the harder it became to manage the thermal load: “Then we will have 800-to-12 V, which is reducing the number of conversion steps, so increasing the efficiency overall. And then 800-to-6 V is really challenging. On the one hand, this reduces the step-down conversion at the GPU level, so it is somehow improving even the load transients and the load dynamics, as we said before. But clearly, this is also creating challenges for the integrity of the bus converter, because thermal management, the huge current to manage, is also at the PCB level.”

Vaughan-Edmunds discussed how thermal management could be the final constraint when collapsing 800V all the way down to these single-digit voltages, “All these data center guys are futuristic, next-generation heat transfer management at the chip level in the liquid cooling pool. We have to get around that. So that’ll be the next challenge: how do you dissipate that power with heat management?”

VPD

AI accelerators are pushing towards multi-kilowatt thermal design power (TDP) with thermal design currents (TDCs) stretching towards 8,000 A per processor, supporting sub-1 V core voltages. Furthermore, the AI and HPC industry is shifting towards 3D heterogeneous integration (3DHI) with chiplets and even panel-level packaging (PLP). There is talk of integrating 50+ chips into a single large unit, creating a mega-chip on the order of 310 x 310 mm and beyond. With these trends, the I²R losses associated with mounting voltage regulators laterally become infeasible at these current densities, calling for the power path to the processor to be as short as possible.

This has led to vertical power delivery (VPD), where mounting configurations can vary between the backside of the AI card’s motherboard/PCB, the bottom surface of the package assembly (land-side), and even embedded within the package substrate (e.g., CoWoS-L, EMIB). However, this vertical integration comes with significant Z-height constraints, with many solutions already on the market at as low as 1 mm.

This last mile of power delivery to the AI accelerator has rapidly become one of the most important aspects of power delivery in the data center, as computing power and server resources (e.g., processors, compute board, and compute tray), as well as cooling systems (e.g., chillers, CRAC/CRAH units, CDUs, etc.), each account for nearly 40% of data center power [1].

The power semiconductor manufacturer’s perspective on this key area of power delivery was of significant interest, particularly regarding the choice between a discrete solution mounted laterally or vertically and integrated voltage regulators (IVRs) designed very close to or within the accelerator package itself.

Deboy offered his thoughts on the matter: “In a discrete solution, you have lateral currents from the power stage into a discrete inductor. This can never be as good as a purely vertical power flow, where you go from the interface through the inductor, through magnetics, and into the load. So vertical power flow, and especially in combination with vertical transistors—silicon-based—is an optimal solution, as the current goes straight into the load rather than routing laterally, creating additional DC losses.”

Deboy continued, “So, in my eyes, high power being beyond 5,000 amps—vertical power flow modules are, in my eyes, the only way, and the discrete solution will disappear.” This tracks, as Infineon uses its Si-based OptiMOS 6 proprietary needle-trench technology in its quad-phase VPD power module, offering 2 A/mm² at a 5-mm height. The module uses chip-embedded packaging that buries the chip within the substrate material.

Scalia continued the conversation with a focus on packaging: “We are talking about encapsulation techniques which are very different from the power modules we’re used to seeing. It might be in hundreds of micrometers. So we are talking about different ways of packaging—stacking devices—and you sometimes need to use hybrid technology, depending on the function it needs to perform. You can use lateral, trench, and many other technologies, such as thin-film caps, directly on the silicon. There are passive integration techniques that need to be encapsulated. I agree—that’s the only way, I think, to address this enormous challenge.”

One critical aspect of VPD solutions is the need to contend with a field of decoupling capacitors to rapidly respond to transients, holding the voltage steady before the regulator can respond. As Scalia noted, many vendors have developed techniques to embed capacitors within the package substrate or even in the processor substrate.

Another critical aspect of converter energy storage is the inductor, which actively regulates the output voltage. These tend to be bulky, which is why vendors are addressing this through a variety of approaches, including thin-film integrated inductors, increasing the switching frequency to the point where magnetics can be shrunk and less capacitor storage is required to respond to transients. However, the transistors themselves must enable faster switching within a smaller die area while maintaining a low R_DS(ON)to carry hundreds of amps with minimal losses. The VPD and IVR market must address wafer-level packaging (WLP), transistor optimization, and passives integration challenges in order to effectively meet the current density requirements of next-generation AI accelerators.

Fabrizio offered a perspective on the potential VPD roadmap, noting that 3DHI will be realized for AI accelerators, enabling tight integration of multiple chiplet technologies across different process nodes. Fabrizio stated: “There are several options—die-side lateral, or land-side vertical co-placement, or even in the substrate. But what we also see in the market in this roadmap is clearly the 3D-heterogeneous integration, or fully integrated IVR with 3D-heterogeneous integration—and the possibility to integrate the vertical power delivery in the interposer, for instance.”

Fabrizio continued: “And here, what we see is the demand from our customers for an end-to-end approach—so we need to cooperate with hyperscalers, with inductor makers, or with passive component makers to see the possibility of integrating those kinds of components, also having embedded technologies on top of the products we provide.”

The general consensus was that effective power delivery to the core is an area that will continue to require far more collaboration; this essentially becomes co-development when voltage regulation becomes integrated at the package level. Power electronics engineers then have to work with IC designers during the SoC’s architectural phase to develop a method to efficiently deliver power to the processor.

Related Content

References

As Generative AI Asks for More Power, Data Centers Seek More Reliable, Cleaner Energy Solutions.” Deloitte Insights, Deloitte, 2025, www.deloitte.com/us/en/insights/industry/technology/technology-media-and-telecom-predictions/2025/genai-power-consumption-creates-need-for-more-sustainable-data-centers.html.

The topic of “AI Data Centers and Their Impact on Power Electronics” will be discussed in a panel during the PowerUP Virtual Event on September 9 – 10. Click here to learn more and register!

The topic of “Vertical Power Delivery (VPD): Challenges and Opportunities” will also be discussed during Aspencore’s Power Electronics Forum at Electronica 2026. Stay tuned to learn more!

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