PowerUP: Panel Discussion: The Gate Driver Problem – Extracting the Most Out of WBG

This session is moderated by Aalyia Shaukat, Editor-in-Chief of Power Electronics News.

Gate driver design is one of the most consequential bottlenecks in extracting WBG performance. GaN and SiC power devices are more difficult to drive than their silicon counterparts, as gate bias windows are narrower, switching transients are faster, and the consequences of getting it wrong are more severe. This panel covers different design philosophies in gate-driver design, such as: Does intelligence belong in the gate driver or the controller? Is monolithic integration actually winning, or is discrete still the right answer for cost-effective, high-performance designs? How much should a gate driver compensate for an imperfect PCB layout—and should it have to? And as WBG pushes toward faster switching and higher voltages, is the gate-driver ecosystem keeping pace, or quietly becoming the ceiling?

Panelists:

• Karsten Düchting, Senior Manager of Strategic Marketing, Allegro MicroSystem
• Thomas Ferianz, Distinguished Engineer System Architect, Infineon
• Asa Kirby, Senior Product Line Manager for Power, Skyworks
• Duke Walton, Sr. Manager, Product Line Marketing, HV Drivers, Microchip

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