Blog Review: Nov. 11

Synopsys’ Charlie Matar finds that interconnects are becoming more influential components of both the silicon and system architecture, with AI infrastructure compute scaling only if data reaches the right processor at the right time at an acceptable power cost.

Siemens’ Bhanu Pandey warns that floating nets in analog power-down circuits represent a hidden reliability risk that can evade even the most rigorous conventional verification flows.

Cadence’s Pratik Kumar Gupta shows how Adaptive Traffic Profiles help ascertain whether an interconnect will sustain the bandwidth of real traffic demands.

Arm’s Emanuele Rocca highlights security features designed to mitigate Control Flow attacks, in which successful exploits overwrite the return address of the function currently executing or the target pointer of an upcoming jump with the address of a memory area controlled by the attacker.

Keysight’s Ricardo Verdeguer Moreno digs into three macro trends driving the market for position, navigation, and timing technologies: an increased focus on resilience and anti-spoofing, low Earth orbit services, and lunar navigation.

Bodewell Group’s Dean Freeman shares insights from the recent SEMI Market Symposium, including the influence that AI is having on the semiconductor industry, and how it will drive the industry and economics past the $1.5 trillion mark to $3 trillion in revenue over the next decade.

Plus, check out blogs featured in the latest Automotive, Security & AI and Test, Measurement & Analytics newsletters:

Technology strategy advisor Geoff Tate finds that exponentially increasing AI compute performance requires exponential interconnect speeds.

Onto Innovation’s John Chang outlines how yield prediction technology can reduce trial and error in advanced packaging lithography.

Rambus’ Maxim Demchenko explains why the location of network security functions is now a critical architectural decision.

Imagination’s Mario Florea outlines a reusable optimization approach for engineers building GPU compute kernels.

Siemens EDA’s Muhammad Hassan, Mahmoud Mahany, and Mohamed Saleh detail why accurate signal integrity analysis must account for interactions across different interconnects, package transitions, and neighboring high-speed channels.

Cadence’s Michael Tran examines what’s needed to prove the automated driving system works safely.

Intel Foundry’s Prashanth Aprameyan notes that power delivery, connectivity, advanced packaging, and supply chain resilience are emerging as the primary constraints on AI scaling.

PDF Solutions’ John Kibarian explains why AI is the most consequential shift the semiconductor industry has faced.

Teradyne’s Matthew Knowles shows why it’s so important to align the design and test ecosystems.

Infineon’s Maya Chou digs into at the benefits of a separate bias regulator dedicated to the gate driver.

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