Etch-Free GaN: Hydrogen Plasma Passivation for HEMTs, Monolithic ICs, and Schottky Diodes

The use of hydrogen plasma treatment has been shown to create several benefits in the performance, stability, and monolithic circuit integration of gallium nitride (GaN) power devices.

Passivation of p-GaN with hydrogen plasma

Shuji Nakamura and his colleagues at Nichia Chemical Industries Ltd., Japan first reported on the effects of annealing a magnesium (Mg) doped p-GaN layer in an ammonia (NH₃) ambient in 1992. High-resistivity films were obtained at temperatures above 400°C when the NH₃ dissociates to produce atomic hydrogen (H). Such an effect was not seen with a pure nitrogen ambient anneal. This indicated that the H creates hole compensation within the p-GaN layer. Subsequent research by others indicated passivation of the Mg acceptors through the formation of neutral Mg-H complexes, creating a large decrease in hole concentration in the near-surface region. 

A key benefit of using H plasma treatment to create a high-resistivity layer is that device formation can largely avoid etching this layer at the surface. Etching creates dangling bonds and interface states that can severely affect the device performance. A planar process achieved through plasma treatment can also be simpler and avoid step-coverage issues of overlying films. Below are a few examples showing the advantages of the H plasma process in GaN device fabrication.

Improved GaN HEMT performance and stability

A common method to create an enhancement-mode (e-mode) GaN HEMT device is the use of a p-GaN gate. The p-GaN layer shifts the Fermi level, effectively removing the intrinsic two-dimensional electron gas (2-DEG) under the gate at 0 V gate bias. The 2-DEG in the access region (i.e., the region between the gate and source/drain electrodes) needs to be recovered. This can be done by etching away the p-GaN layer in this region. 

Ronghui Hao and colleagues conducted a study that compared the etching process to the H-plasma-treated p-GaN/AlGaN/GaN HEMT device. In this process, the gate metal provides a self-aligned mask to the H plasma, ensuring high-resistivity layer formation only in the access regions. The plasma-treated device exhibited a higher transconductance (g_m) and saturation current at a similar threshold voltage (V_th ~ 1.75 V), as well as a lower gate leakage compared to the etched device. 

Li et. al. [1] compared the stability of the devices fabricated this way. The V_th shift of the device was measured as the drain voltage was ramped up under both soft and hard switching conditions. 

As shown in Figure 1, the H-treated devices show significantly improved stability. The current collapse was only 5% for the H-treated devices, while the etched devices degraded by 48%. Improved surface states and hence a lower rate of hot-electron-based trapping in the H-treated devices are the reason for this improvement. 

Optimization studies for the H-treatment in GaN HEMTs have been performed by several groups. One such study found that a lower RF power results in a lower reverse leakage current, while a post-plasma rapid thermal anneal (RTA) at 350°C was shown to create the best tradeoff in low reverse leakage and a high forward drain current. 

Creation of GaN HEMT direct-coupled FET logic (DCFL) circuits

Monolithic integration of low-voltage (LV) enhancement- and depletion-mode (e-/d- mode) HEMTs, 2-DEG resistors, and metal-insulator-metal (MIM) capacitors with the HV HEMT power device enables a DCFL integrated power converter. The high-power conversion efficiency of GaN makes these converters an attractive alternative to Si-based integrated bipolar-CMOS-DMOS ICs. 

Such levels of integration can be used to produce power management ICs (PMICs) and multi-level converters with integrated drivers, sense/compare logic, and fault detection. Monolithic integration can better leverage GaN’s high switching-speed capability with fewer parasitic components than multi-die solutions. 

Fan Li and colleagues have demonstrated an integrated 48 V DC-DC buck converter using a process flow that included H-treatment. The D-mode device was treated to convert the entire p-GaN gate layer into a high-resistivity layer, thus restoring the 2-DEG over the entire device, as shown in Figure 2. The e-mode device undergoes H-treatment only in the access regions, as described in the previous section. 

The H-plasma-treated e-mode device showed a significantly improved breakdown voltage (BV >1300 V) compared to an etched version (BV < 600 V). The devices and circuit were simulated with a calibrated Advanced Spice Model (ASM). The converter showed good performance operating at a switching frequency of 1 MHz, demonstrating the feasibility of this process flow in constructing advanced GaN ICs. 

H-Plasma edge termination in Schottky barrier diodes (SBDs)

A quasi-vertical GaN-on-Si SBD

SBDs can be essential components in power conversion circuits, and the creation of GaN SBDs presents a path to monolithically integrate these with the HEMT device. 

Xuan Liu and colleagues demonstrated a quasi-vertical GaN-on-Si SBD that used a graded p-GaN junction adjacent to the top n-GaN anode Schottky contact. The p-n junction screens the Schottky contact from high electric fields. Controlled lateral diffusion of H into the p-GaN layer grades this junction termination and further reduces electric-field crowding. 

The H-plasma treatment reduces etch-based leakage compared to a pure p-n junction edge termination that is mesa-etched. The reverse breakdown of a GaN SBD without any edge termination was measured to be 140 V. 

The p-GaN edge termination increased this to 440 V. H-treatment further improved this to 477 V, with lower reverse leakage. A 60-s anneal at 450°C post H-treatment further increased the BV to 500 V. The anneal created lateral diffusion and was shown by simulations to lower the peak surface electric field by almost a factor of two compared to the unannealed H-treated SBD.

Hydrogen guard array termination

Professor H. Fu and his team at Arizona State University, along with colleagues at the University of Utah, USA, took this concept further by demonstrating an AlGaN/GaN SBD with a BV of 9.5 kV using H-treated edge termination. The structure consisted of a p-GaN/AlGaN/GaN stack. 

A novel hydrogen guard array termination (H-GAT) was used on this lateral SBD, which consisted of a circular array pattern of the p-GaN active layer, surrounded by the H-treated resistive layer. 

The circular pattern density increases on the anode side, with a larger H-treated area toward the cathode terminal that contacts the 2-DEG at the heterojunction. The goal is to distribute the electric field under high reverse bias so that it covers the whole surface between the cathode and anode. 

The H-GAT SBD structure had reverse leakage at least two orders of magnitude lower than the structure without this process, with a leakage level of ~10^-6 mA/mm at 3 kV. A specific on-state resistance (R_{ON, SP}) of 118 mΩᐧcm² was measured on the optimized structure that had a BV of 9.5 kV, making it the SBD with one of the best BV²/ R_{ON, SP} metrics amongst WBG semiconductors in the multi-kV class. 

Cover image: Adobe Stock

References

1. F. Li, Y. Liang, Y. Zhang, Y. Huang, A. Li, Y. Zhu, C. Yu, Y. Wang, S. Wu, G. Yu, Y. Pei, B. Zhang, and W. Liu, “Monolithic Investigation of Hydrogen Plasma-Treated and Etched p-GaN Gate HEMTs Under OFF State Drain Stress,” IEEE Transactions on Electron Devices, vol. 71, no. 6, pp. 3801–3804, 2024.
2. F. Li, S. Wu, A. Li, Y. Zhu, M. Cui, J. Gu, P. Zhang, Y. Zhao, H. Wen, and W. Liu, “Investigation on the Dynamic Characteristics of Hydrogen Plasma Treated p-GaN HEMTs Circuit Using ASM-GaN Model,” IEEE Journal of the Electron Devices Society, vol. 12, pp. 457–463, 2024.

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