Inside Navitas’ Claros IVR: How Digital Control Scales Power Delivery to Thousands of Amps

Navitas closed the Claros acquisition in early October 2026, calling it a “defining step” in the Navitas 2.0 transformation with a new IVR business unit headed by Dan Kultran as VP and GM and former CEO of Claros. According to a recent webinar, “Breaking the AI Infrastructure Power Wall: Navitas 2.0 Completes the Grid-to-XPU Power Portfolio with Claros Acquisition,” hyperscalers increasingly own the entire power chain, from the grid to the xPU (e.g., CPU, GPU, TPU, etc.). 

Companies like Infineon, Monolithic Power Systems, Analog Devices (ADI), GlobalFoundries, Renesas/Flex, Delta, and more are competing with their own vertical power delivery (VPD) solutions. Many are traditional power electronics companies with established Si, GaN, and/or SiC portfolios, now shifting into last-mile data center power delivery as an extension (Figure 1). 

The spotlight on PoL 

In data centers, PoL conversion has, in many cases, shifted from lateral power delivery (LPD) to VPD to cut resistive losses from a longer electrical path. “Lateral power delivery can lose up to 30% of the power, power that never reaches the processor,” said Kultran. 

As shown in Figure 2, modern GPUs are seeing a power rise from ~1.4 kW in 2025 to 4.4 kW in 2028, to well above 10 kW by 2030 and beyond. At sub-1V core voltages, this means thermal design currents (TDCs) peak in the thousands of amps. 

Some vendors, like Claros/Navitas, Ferric (soon to be part of onsemi), and Empower Semiconductor/ADI, are moving to integrated voltage regulators (IVRs) mounted on the PCB backside directly beneath the processor, while others target the package itself (on the land side, on the interposer, or embedded within the package substrate), sometimes known as embedded power delivery (EPD) (Figure 3). The aims are to cut I²R losses in the power delivery path, shorten the low-inductance path to the processor, and reclaim the area that board-level decoupling capacitors occupy.

The VPD market faces some of the most intensive integration challenges, adding control, power, and magnetics while tightly balancing thermals/packaging, efficiency, size, and cost, but, according to Chris Allexandre, CEO of Navitas, it offers higher margins.“Our identified 2030 TAM [total addressable market] expands from the original $3.5 billion GaN and SiC base to more than $8 billion, including new JFET technology and Claros IVR,” said Allexandre during the webinar. 

A deeper dive into Claros’ IVR technology

Beyond the recent webinar, Power Electronics News sat down with Dan Kultran in an exclusive interview to learn more about the IVR technology.

According to Kultran, scaling happens at two levels: “how many building blocks we put into a single chip, and how many chips we combine at the system level.” As shown in Figure 4, the basic unit is a 10-A building block that can be combined into 40-A or 160-A chips. The 40-A chip, which integrates all passive components, measures 3.3 × 3.6 mm and delivers a current density of about 3.4 A/mm². 

According to Kultran, Claros reaches that density through advanced 3D heterogeneous integration at the package level, combining the digital controller (PowerArray), power FinFETs, inductor (NavCoil), and capacitors (NavCap) on an advanced film substrate in a single package (Figure 5). The approach draws on the team’s RF background, where fine-geometry packaging and 3D electromagnetic modeling are standard practice. “The stuff that’s being done in RF is now being implemented in the power domain,” Kultran said.

At the system level, chips are combined through the PowerArray architecture. Every chip carries the same controller; on the board, one is configured as the master and the rest act as followers. A single master coordinates up to 64 chips in one voltage domain, delivering ~2,500 A with 40-A chips or ~10,000 A with 160-A chips. For scale, 64 of the 40-A chips occupy roughly 760 mm² (~1.18 in²), before any spacing between chips. 

Further, a host can address up to 26 masters, each running its own voltage domain, so the theoretical ceiling is ~66,500 A for the 40-A chips (40 A × 64 × 26) and ~266,000 A for the 160-A chips (160 A × 64 × 26).

“You’re not going to get a system that’s 60,000 A,” Kultran acknowledged. Instead, the ability to run up to 26 independent voltage domains reflects how customers’ systems actually draw power. Although processor TDCs reach into the thousands of amps, that current is split across many voltage domains of roughly 700 A to 1,200 A each. “It’s not like 6,000 A aggregating to a single voltage domain,” said Kultran.

40-A and 160-A chips for different voltage domains

Small chips let customers size each rail from the same part. “A 1,000 A part probably has way too much waste,” Kultran said. A 200-A I/O rail, for example, would otherwise need a second, smaller regulator. “You qualify a single part, and you use all of those same parts in the system. Much easier design for our customer, and more cost-effective, because you’re dealing with a single SKU.”

When a single domain outgrows a 64-chip array of 40-A parts, Claros scales the chip instead. “Some customers go, ‘What if I have a 3,000 A domain?’ Then I say, ‘No problem. I’ll scale up the chip. Instead of a 40 A chip, I’ll give you a 160 A chip,’” said Kultran.

Dropping the external controller

Today’s processor power delivery is typically built on multiphase buck converters: according to Kultran, the conventional approach scales through a single controller that sits off to the side, driving many smart power stages (SPSs)—ICs that integrate the high- and low-side FETs, gate driver, and current sensing for one phase.

He argued that the industry’s answer for more current has largely been more phases and bigger power stages, but there is a practical ceiling on how many phases an external controller can manage. “So it’s not really conducive to scale, right? But you know what? For lack of a solution, people are actually trying to cram it all in. So you’re starting to see 16-, 32-phase controllers, doubling the SPS size,” said Kultran.

This is because every phase needs well-matched high-speed signals from the controller, plus current-sense lines back. Under the GPU, this routing competes for PCB area and BGA balls that the xPU may need for other signals, ground, and thermal structures. 

According to Kultran, each Claros IVR chip has its own controller (Figure 5), so the matched high-speed signals that once ran from controller to power stages now stay inside the chip. Only communication, input, and output lines leave it. “It’s definitely going to help you reduce the number of layers you need, and then you can use all the extra layers for something more useful, like I/O or something else,” he said. Integrating the controller is “quite hard to do, especially if you want density,” Kultran noted, and not every IVR on the market does so. 

High-speed digital bus and current sharing

According to Kultran, analog current-sharing schemes typically stop at about 8 converters, limited by accuracy and noise. “In the past, people have been sharing current through the analog domain, which has the drawback of limiting the number of converters that can share,” he said. “Analog has a lot of drawbacks in terms of accuracy and noise.”

Claros instead shares current digitally over its own high-speed bus. Each die senses its current with SenseFETs and digitizes it with an on-die ADC, so the signal is digital from the start. “Because we’re already sensing everything in digital, why convert to analog and then back to digital again?” Kultran said. “We sense everything in digital and then just send it out in digital.”

During a fast load step, “by the time the last guy sees the transient event happen, he’s like, ‘Oh, it’s too late,’” Kultran said. The bus architecture is designed to keep latency low enough to meet customers’ tight transient requirements, which caps each array at 64 chips. 

800 V→6 V→core

Navitas has described the IVR as having a 3:1 conversion ratio, but Kultran said that figure is used loosely. “Our input is 3.3 V nominal. The output that the customers are using is typically 0.8 V and below,” he said. “It’s 3.3 divided by 0.8, which is a little bit more than a 4:1 conversion ratio.” 

As customers move to 2- to 3-nm processes with core voltages near 0.6 V, the ratio climbs to about 5.5:1. Kultran said 3.3 V is “the highest input voltage you can get today on IVR.” Navitas is already developing a version that takes 6 V directly down to the core.

This lines up with Navitas’ product roadmap. In October 2026, Navitas and Microchip released an 800-V-to-6-V reference design, building on the power delivery board (PDB) Navitas unveiled at NVIDIA GTC in March. With these technologies, Navitas could deliver power from the 800-V bus to the processor core in just two conversion stages. “Once it’s 800 V, all the way down to 6 V, which is sort of the future,” said Kultran.

The trade-off of the higher conversion ratio is the converter’s own efficiency, which Kultran acknowledged “might be sub-90%.” “It is important to have decent efficiency for the converter itself, but that’s not the full story, because it’s a system problem,” said Kultran.

The higher ratio matters at the system level. Resistive (I²R) losses scale with the square of current, so raising the input voltage sharply cuts losses. A 2:1 converter reduces those losses by 4×; at just over 4:1, the reduction is roughly 16×. Navitas’ planned 6-V version would reach 6:1 for a 1-V core, a reduction of roughly 36×. According to Kultran, the 6-V IVR will still fit under the processor. 

P-IVR and E-IVR

The technology ships in two forms. Package IVR (P-IVR) sits beneath the processor in place of bulkier VPD modules, while embedded IVR (E-IVR) integrates chiplets and passives directly into the processor substrate. “We developed both products because customers need improvement before embedded architectures are ready,” Kultran said. “People say you can’t have fast, low-cost, and good. I try to blend the triangle into a circle so you can have all three.”

Cover image: Navitas Semiconductor

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