A System-Level Approach To Protecting 3D-IC Signal Integrity

By Muhammad Hassan, Mahmoud Mahany, and Mohamed Saleh

The semiconductor industry is rapidly transitioning to chiplet-based architectures to meet the performance, bandwidth, and power demands of AI and high-performance computing (HPC). Technologies such as TSMC CoWoS, SoIC, Samsung I-Cube, X-Cube, Intel EMIB, and Foveros enable designers to integrate multiple compute, memory, and I/O dies into a single package, dramatically increasing system capability while reducing development risk.

As these architectures become more complex, signal integrity has emerged as a critical design challenge. High-speed die-to-die (D2D) interfaces, dense microbump arrays, silicon interposers, TSVs, and advanced package substrates introduce electromagnetic effects that can significantly impact performance, power efficiency, and product yield.

Traditional design methodologies that verify dies, packages, and interconnects independently are no longer sufficient. Success requires a system-level approach capable of validating complete communication channels spanning dies, interposers, package substrates, and memory stacks.

Why signal integrity is challenging in 3D-IC/advanced packaging

Signal integrity ensures reliable communication between heterogeneous chiplets and HBM stacks operating at high data rates. Unlike traditional 2D SoCs, 2.5D/3D systems—such as TSMC Chip-on-Wafer-on-Substrate with a Silicon Interposer (CoWoS), SoIC, and Chip-on-Wafer (CoW), together with Intel Embedded Multi-Die Interconnect Bridge (EMIB), EMIB-T, and Foveros technologies—feature multiple interconnect structures, including D2D interfaces, microbumps, TSVs, RDLs, interposers, bridges, and advanced substrates. Each transition introduces impedance discontinuities, parasitic coupling, and return-path disturbances that cross process nodes and dense interconnects. Mitigating these effects requires a system-level view of the entire communication channel rather than isolated analysis of individual blocks.

Fig. 1: TSMC’s CoWoS-S on the left and Intel’s EMIB on the right.

Advanced packaging increases electromagnetic complexity

Advanced packaging platforms introduce sophisticated, highly coupled routing topologies. At multi-gigahertz frequencies, accurate SI analysis must account for interactions across vertical interconnects, interposers, silicon bridges, package transitions, and neighboring high-speed channels. Unlike traditional PCBs, D2D interfaces exhibit distinct mathematical loss properties.

Linear frequency roll-off: Loss scales steeply and linearly as skin-effect dominates the microscopic wires.
Phase distortion (dispersion): Channels shift from low-frequency resistive (RC) behavior to high-frequency transmission line behavior, triggering severe inter-symbol interference (ISI).
Crosstalk dominance: Sub-micron routing gaps 0.5 µm to 2 µm cause capacitive and inductive coupling to inject more noise than physical dielectric attenuation.
S21 transition: Insertion loss plots show a downward roll-off, transitioning from low-frequency RC loss to high-frequency substrate-dominated attenuation.

Fig. 2: Typical lossy channel loss profile in silicon interposer.

The channel’s low-pass frequency response heavily attenuates high-frequency harmonics, blunting the signal’s rise and fall times. In the time domain, this high-frequency roll-off manifests as severe ISI and increased jitter, directly shrinking the vertical eye height (Y) at the receiver pad as shown in Figure 3.

Fig. 3: Received signal highlighting channel bandwidth limitation.

UCIe raises the bar

The emergence of advanced D2D communication standards is placing even greater emphasis on early signal integrity verification. Universal Chiplet Interconnect Express (UCIe) is an open industry specification defining physical layers, protocols, compliance, and multi-vendor interoperability for 2D, 2.5D, and 3D packages. It offers up to sub-2 ns physical layer latency, a highly scalable modular architecture, and maximum cost-effectiveness by mixing heterogeneous chiplets. The specification fundamentally bifurcates into two packaging tiers.

Advanced packaging (2.5D interposer/bridge): Optimizes for ultra-short reach (<=2 mm) at up to 64 GT/s per pin (UCIe 3.0), utilizing 64 single-ended mainband data lanes per module. It routes signals unterminated at the receiver to hit an ultra-dense energy efficiency of 0.25 pJ/bit.
Standard packaging (2D/laminate): Extends channel reach up to 25 mm at 16 to 32 GT/s per pin across 16 single-ended mainband data lanes per module. It utilizes 50-ohm parallel ground terminations at the receiver to dissipate long-trace reflections at an efficiency cost of 0.5 pJ/bit.

Enforcing the UCIe open standard shifts validation onto strict hardware-level compliance protocols; channels must maintain an extraction frequency response (S₂₁) strictly above a mandatory voltage transfer function mask.

Figure 4 compares representative UCIe bump maps for the two packaging tiers: UCIe-AP (advanced packaging) and UCIe-SP (standard packaging), illustrating their different bump densities and Tx/Rx lane organizations.

Fig. 4: UCIe bump maps: (a) UCIe-AP bump map and (b) UCIe-SP bump map.

Complex interposer stackups and EDA translation challenges

Unlike traditional fiberglass PCBs that tolerate minor thickness variations and use coarse trace geometries (>50), silicon interposers utilize a non-laminate, planarized back-end stack-up derived from semiconductor foundry manufacturing. Microscopic copper traces (0.5 to 2 µm) are embedded within a perfectly flat matrix of deposited silicon dioxide (SiO2) or low-k dielectrics. Because the interposer bridges sub-micron chiplet nodes, any surface waviness or conformal warping causes lithographic mask misalignment and snaps the microscopic wires. Consequently, foundries rely on expensive chemical vapor deposition and chemical mechanical planarization to polish every single layer down to an absolute mirror-like plane.

Accurately modeling these structures requires automated workflows to ingest highly detailed stackup data. Foundries distribute this structural data in specialized semiconductor formats, like iRCX, MiPT, and ITF. Effortlessly converting these formats into native EDA electromagnetic (EM) solver inputs is highly challenging. The target EM software must map the 2D process profiles into precise 3D boundary-value solver definitions while maintaining computational efficiency. Attempting this translation manually introduces severe risks of human error, as omitted layer rules or misconfigured thickness parameters create critical modeling inaccuracies later in the signal integrity sign-off phase.

GDSII/OASIS: Interposer layout and EM simulation challenges

Silicon interposers utilize GDSII and OASIS formats because they are manufactured using standard semiconductor foundry lithography rather than mechanical PCB drilling and routing. These sub-micron features (0.5 to 2 µm trace widths) require the exact geometric language of the chip foundry optimized for advanced silicon manufacturing.

Importing raw foundry GDSII or OASIS layout data into 3D EM simulation engines triggers three severe performance bottlenecks:

Absence of 3D stack-up context: GDSII and OASIS are purely 2D polygon coordinate maps containing no data on Z-axis height, dielectric thickness, or material loss tangents. Engineers must manually merge a separate tech file (.tch, .ict, .xml) to construct the physical 3D model.

Fractured polygon mesh explosion: Tape-out formats do not support true smooth curves. Circular micro-bumps and TSVs are fractured into hundreds of microscopic, sharp-edged trapezoids. This triggers a computational mesh explosion that overwhelms simulator memory (RAM) upon ingestion.
Hierarchy versus simulation flattening: GDSII and OASIS compress file sizes using deeply nested hierarchies (referencing one macro cell thousands of times). Because EM field solvers must calculate the entire continuous electrical signal path and surrounding ground return paths, the tool must “flatten” these cells, completely stripping away the file’s native layout compression and causing massive data inflation.

Unified 3D-IC signal integrity solution

Siemens’ Innovator3D IC solution suite addresses these complexities by providing a unified, system-level environment that aggregates several proven technologies into a seamless workflow spanning architecture exploration, electromagnetic extraction, channel simulation, protocol compliance verification, and final system-level signoff.

Innovator3D IC Integrator for rapid multi-die architectural floorplanning and integration
Innovator3D IC Integrator Layout for physical layout design, substrate trace pathing, and assembly closure
Innovator3D IC Protocol Analyzer for automated D2D interface compliance checking
HyperLynx SI/PI for comprehensive high-speed channel and power integrity simulation
xCalibrate for automated foundry stackup extraction and tech-file generation
Calibre DESIGNrev for high-performance layout manipulation and property annotation
Aprisa for tapeout-quality digital physical implementation and routing

Fig. 5: Signal integrity workflows for 3D IC using Innovator3D IC Integrator cockpit.

As AI and HPC architectures rapidly adopt chiplet designs built on advanced platforms—such as TSMC CoWoS, SoIC, and Intel EMIB, EMIB-T, and Foveros—signal integrity verification must evolve from component-level validation to full system-level channel analysis. High-speed D2D interfaces like open-standard UCIe and proprietary NVLink-C2C demand high-precision EM modeling, strict protocol compliance verification, and package-aware channel optimization.

Siemens delivers a comprehensive, unified signal integrity platform. This end-to-end workflow enables early architectural exploration, accurate 3D EM extraction, automated stackup compilation, and robust protocol compliance verification—ensuring confident, first-time-right signoff for next-generation 2.5D and 3D IC designs.

To learn more about Siemens’ end-to-end 3D IC solution can help your team achieve first-pass silicon success while accelerating time-to-market, please download the new whitepaper, 3D-IC signal integrity: From silicon interposers to system signoff.

Mahmoud Salah Mahany is a senior software development engineer in Central Engineering solutions at Siemens focusing on signal and power integrity, developing and optimizing SI/PI flows for 3D ICs to support advanced nodes and complex semiconductor ecosystems. He received the B.Sc. degree in Nanotechnology and Nanoelectronics from Zewail University of Science and Technology in 2018 and the M.Sc. degree in Electronics and Communications from the American University in Cairo in 2024.

Mohamed Saleh Abouelyazid is a senior technical manager and R&D architect in Calibre, Design to Silicon Department at Siemens since 2009. Mohamed has authored or coauthored publications and patents focusing on physical verification, data modeling, and electronic design automation. He received the B.Sc. and M.Sc. degrees in electronics engineering from the Faculty of Engineering, Cairo University, Cairo, Egypt, in 2009 and 2013, respectively, and the Ph.D. degree from the School of Sciences and Engineering, The American University in Cairo, Cairo, in 2022.

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