Thin Dielectric Substrates for WBG Module Packaging

The substrate in a power module plays a vital role in creating an electrical barrier, supplying mechanical support, and providing a thermal path for heat dissipation. The increased power density in wide-bandgap (WBG) semiconductor modules can impose greater challenges for the substrate to meet these key requirements and not limit the intrinsic advantages of WBG power devices in high-power and/or high-frequency power conversion applications.

Substrate requirements for WBG power modules

Silicon carbide (SiC) and gallium nitride (GaN) WBG semiconductor devices have lower specific on-resistance (R_ON-sp) for the same breakdown voltage. This enables smaller die with reduced parasitics, lower switching losses, and higher operating frequencies.

Lower losses and/or higher conversion frequencies, in turn, allow for smaller passive components and/or simpler cooling. Both factors can create significant advantages in system-level power densities.

Thermal management plays a critical role under these higher-power-density conditions. A maximum semiconductor junction temperature (T_jmax) of 150°C to 175°C is typical for reliability reasons. For a given T_jmax, frequency upscaling can be done only if the R_ON-sp benefits of WBG devices are achieved in conjunction with improvements in the net thermal resistance, R_thj-a, the junction-to-ambient thermal resistance.

Semiconductor thermal properties, die design, and architecture can create some of the initial constraints in R_thj-a. For example, a vertical SiC MOSFET, with improved intrinsic thermal conductivity and an architecture that allows a larger semiconductor volume for current flow, has advantages over the lateral GaN-on-silicon HEMT.

The lower substrate conductivity and a thinner current-conducting channel with a non-uniform electric field in the GaN HEMT can create localized heat spots that can limit the overall system thermal performance. Gallium oxide, an ultra-WBG material with poor thermal conductivity, is an example of how a basic semiconductor property can limit its potential use in high-power applications.

The packaging plays a next-level role in the module R_thj-a. This includes the die-attach process, the substrate on which the die is mounted, and the heatsinking. The substrate provides three vital functions:

• Thermal management: High thermal conductance in the substrate allows rapid heat removal from the semiconductor junction on one side of the substrate to the heatsink on the other side. High thermal capacity enables the absorption of more thermal energy for a given temperature rise.
• Electrical isolation: Isolation of high potentials, as well as providing minimal capacitive coupling on fast-switching transitions, are key to utilizing WBG semiconductors to their full potential. Partial discharge (PD) and electromagnetic interference (EMI) can be limiting factors.
• Thermomechanical robustness: The ability of the substrate and the die attach/metallization to withstand thermal-cycling-related mechanical stress is a big factor in preventing reliability failures. High mechanical flexibility of the substrate and the coefficient of thermal expansion (CTE) matching to the metal and semiconductors in close contact with it ensure structural integrity under the full operational temperature range.

Substrate selection typically involves trade-offs. A thicker substrate has higher voltage-withstand capability but with the penalty of lower thermal conductance.

Cost and reliability can create important trade-offs. Insulated metal substrates (IMSes), where a ceramic-polymer-blended isolating layer separates a copper (Cu) foil-based circuit layer from the heatsink baseplate, are cheap but have a lower thermal conductivity in the 1- to 10-W/m·K range and a stronger tradeoff in terms of much worse PD and EMI if the polymer is thinned to improve thermal performance.

Direct-bonded Cu (DBC) uses a ceramic base such as alumina (Al₂O₃) or aluminum nitride (AlN). They have robust high-temperature operation and are widely used in high-power WBG power modules. Low capacitive coupling and good voltage isolation are ensured, especially for thicker substrates such as 15 mils of Al₂O₃, but with a trade-off in heat-removal capability.

AlN has improved thermal performance compared with Al₂O₃ but at a cost that can be 3× to 4× higher. Mechanical stress at the ceramic-Cu interface created from the CTE mismatch (5–6 ppm/°C for Al₂O₃ versus ~16–18 ppm/°C for Cu) limits temperature cycling of DBC modules to <1,000 cycles. Active metal brazing, where a Cu foil is brazed onto a silicon nitride (Si₃N₄) substrate, provides improved thermal-cycling performance but at an even higher cost than DBC.

eIMS substrate using thin ERCD

Organic epoxy resin composite dielectrics (ERCD) provide an alternative substrate choice to traditional ceramics. Risho Kyogo, a Japanese manufacturer of electrical insulation materials, produces thin ERCD films under the Risholite brand.

These thermally conductive laminates comprise resin with Al₂O₃ and AlN ceramic fillers. They have a high glass transition temperature (T_g ≥ 250°C), strong peel strength, a thermal conductivity that ranges from 8 to 10 W/m·K, and a dielectric breakdown field strength in the 40-kV/mm range.

The AC-7210N ERCD film is 120 µm thick, hence providing a dielectric breakdown voltage of >5 kV. Figure 1 compares some basic characteristics of this ERCD film with Al₂O₃ and AlN ceramic substrates.

Though the thermal conductivity of the ERCD is lower than the ceramics used for the comparison, the thinner layer translates to a net thermal conductance close to a standard, 10-mil Al₂O₃ substrate. A key differentiator is the cost, with the ERCD almost a factor of 10× lower than Al₂O₃. The minimum bending radius, based on the bending stress, is also much lower due to its reduced thickness.

Wire-bond-less double-sided-cooled (DSC) power modules create improved thermal and reliability advantages, but the use of traditional DBC with thick Cu foils (~300 µm) forces a wide Cu trace design rule, with minimum line/space in the 1-mm range.

Thicker substrates also increase the module form factor. The use of thinner substrates such as ERCD in a DSC module takes advantage of the film’s high dielectric strength along with a reasonable thermal conductance.

Sourish Sinha from the Ford Motor Company, along with a team from North Carolina State University, presented the design of a GaN ERCD-based DSC integrated power module (IPM). The substrate starts with the AC-7210N film. Brigitflex, a circuit board manufacturer, created an epoxy IMS (eIMS) substrate by trimming the ERCD sheet to the required size and then creating a 4-oz. Cu trace (140 µm thick) for the power device placement on one of its sides.

This trace has a minimum line/space design rule of about 0.1 mm, much smaller than that of a typical DBC. The opposite side of the ERCD had a 2-mm Cu baseplate.

The authors conducted a thermomechanical simulation study comparing a DSC module with DBCs at the top and bottom of the power device, eIMS on both sides, and a combination of DBC and eIMS with placement on either side of the module. SAC 305 solder was used for the die attach to the GaN die, and Cu spacers were used above the GaN die.

The simulation looked at the maximum stress on the GaN die as well as the equivalent plastic strain on the SAC 305. Using a maximum stress criterion of 150 MPa, only the Dual-ERCD and the ERCD/DBC combinations passed the test.

In the case of the DBC, the ceramic-Cu CTE mismatch dominates the stress characteristics. The ERCD has a much better CTE match to Cu, and stress in this case is dominated more by the GaN die-attach bond line.

DSC GaN IPM

Figure 2 depicts a cross-sectional view of the ERCD-based DSC GaN IPM. This includes the GaN HEMTs, gate drivers, and bypass/decoupling capacitors.

It should be noted from Figure 1 that the thinner dielectric contributes to increased capacitive coupling between high-frequency traces and the baseplate metal. This can be particularly harmful in creating high substrate and common-mode currents (I_CM) during high-speed operation in GaN power modules.

The authors used capacitance distribution to lower I_CM. Mutual-inductance cancellation was done through a parallel-plate approach, with current in each plate flowing in the opposite direction. A compact, high-frequency commutation loop (shown by the red dotted lines in Figure 2) design ensured a power-loop inductance of 1.18 nH at 50 MHz, while minimizing the gate loop resulted in a gate loop inductance of only 0.15 nH.

Double-pulse tests of the 30 × 20 × 5.7-mm³ half-bridge module at 400 V, 61 A validated a >40-V/ns dv/dt capability.

Cover image: Adobe Stock

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