Altera Brings FPGAs to Physical AI With Agilex 2X and an Agentic Design Assistant
Altera Corp. has unveiled a new FPGA portfolio, targeting intelligent systems, including physical AI at the edge and the digital AI infrastructure. Supported by a unified agentic AI design flow, the new Agilex 2X FPGA and system-on-chip (SoC) portfolio spans high-performance, mid-range, and power- and cost-optimized devices. The first announced family is the Agilex 27 for high-bandwidth, high-throughput systems.
"Intelligence is reshaping a lot of what's happening in the electronics industry and it's touching every application," said Lux Joshi, senior director, product management, at Altera Corp.
These workloads are evolving faster than ever to meet greater throughput and new functionality demands, and FPGAs are intended for these workload changes, keeping up with the advancements at the hardware level with programmability, he said.
FPGAs also provide hardware adaptability, deterministic processing, and high-speed I/Os, making them suited for physical AI applications.
The growth of physical AI, which require a much richer set of heterogeneous architectures, is a key driver behind the development of the Agilex 2X family, according to Joshi.
For example, robots require heterogeneous architectures that can sense the physical world, process sensor data with low latency, provide high levels of deterministic behavior and functional safety, as well as perform more advanced compute to produce outcomes in the physical world, he explained.
Scalability, architecture innovations, and agentic AI
The Agilex 2X portfolio comprises four device families-Agilex 27, Agilex 25, Agilex 23, and Agilex 22, each optimized for different power- and-cost performance, depending on the application. This allows customers to prioritize different combinations of connectivity, bandwidth, capacity, power efficiency, and overall performance to meet requirements for different applications, ranging from data centers and digital artificial intelligence infrastructure to communications, aerospace and defense, embedded systems, and physical artificial intelligence.
Joshi explained that the three key features of the Agilex 2X portfolio are its scalability, building out multiple product tiers that cover different levels of performance, power efficiency, I/O interfacing, and embedded compute, tailored for different applications; new architectural elements; and a unified agentic AI developer experience based on the QuartusIQ AI Expert Companion.
Agilex 2X builds on Altera's fabric architecture with key innovations such as the 3rd Gen HyperFlex Fabric and new HyperFlow data network. These FPGAs are optimized for performance per watt at the application level, as well as scaling performance and capacity at the high end and low power and I/O density at the other end.
The new portfolio offers enhanced AI tensor DSP blocks to accelerate compute in signal processing applications, the latest Arm cores, high-bandwidth connectivity to support mainstream and next-generation standards, and end-to-end security for data and system integrity. It shares common security and embedded software foundations, including Arm-based hard processors and Nios V soft processors, post-quantum-cryptography-ready secure boot, and functional-safety practices.
The Agilex 2X portfolio is supported by its Quartus Prime software and recently introduced QuartusIQ, which provides an agentic design flow. With these tools, customers can work from common design workflows and reusable IP across every family in the Agilex 2X portfolio, Altera said.
QuartusIQ combines smarter design guidance, specialized chat interaction, agentic design flows, and timing-closure assistance to accelerate an end-to-end design flow. This includes an agent runtime harness that preconditions all queries into an AI model.
The tool can help both experienced FPGA engineers and developers who would not ordinarily choose an FPGA as their first architecture, Joshi said.
Engineers and developers can translate system requirements into a design working from architectural descriptions, block diagrams, drawings, natural-language descriptions, and design constraints. It can build FPGA designs, launch compilation and simulation flows, read reports, identify possible bugs, run timing closure, recommend or apply design changes on its own, and support debugging and test-harness development.
Engineers may allow it to make changes autonomously and return a completed result, or require review and approval between design stages, Joshi said.
It can also work through Visual Studio using a Model Context Protocol connector. Customers using Visual Studio with GitHub Copilot can use the connector to build designs through an agentic workflow. They can use frontier models or open-weight models, including Nvidia's Nemotron model, and may bring their own model access key.
QuartusIQ was trained using more than 20,000 documents, providing more FPGA-specific context than a general-purpose model alone.
Altera reports that QuartusIQ benchmarks show up to 10× faster design creation, reducing weeks or months of work to hours or days. Benchmarks also indicate overall design-cycle improvements of approximately 1.5× and, in some cases, 2×, Joshi said. The largest expected benefits are associated with design creation, timing closure, and debugging.
Agilex 2X family
The Agilex 27 high-performance FPGA and SoC family targets processing- and bandwidth-intensive applications such as digital AI infrastructure, terabit networking, 6G and satellite networks, and aerospace and defense applications. Key features include a high-performance fabric, high capacities, maximum memory bandwidth, and next-generation connectivity for data-path processing, beamforming, and RF processing.
The Agilex 27 portfolio offers high capacity with high memory bandwidth, and high transceiver bandwidth for the most demanding bandwidth- and compute-intensive applications, Joshi said.
This flagship platform highlights several architectural developments, including the 3rd generation HyperFlex fabric and the new HyperFlow data network.
The HyperFlex architecture adds registers throughout the routing fabric, allowing software tools to support more efficient pipeline-register retiming, delivering improvements in design performance and power efficiency. It delivers a 1.8× performance/watt improvement over the previous-generation Agilex 7 products, Joshi said.
Because HyperFlex embeds registers throughout the routing fabric, it allows the Quartus Prime software to re-time and pipeline designs without consuming logic resources. In addition, new adaptive logic module (ALM) modes further enhance logic packing and performance that enables customers to increase performance while fitting into a smaller, lower-power footprint, according to the company.
Agilex 27 also introduces the HyperFlow data network, described as a network-on-chip architecture capable of multi-terabit-per-second data movement across the different interfaces without consuming soft logic resources or introducing routing congestion. Data paths include PCIe to memory or the Arm processor subsystem, and very high-speed transfers from memory into the FPGA fabric.
Joshi explained the architecture alleviates data-movement bottlenecks and supports direct memory access transfers while using less soft logic in the FPGA fabric.
"Agilex 27 also is providing next-generation connectivity from 2× to 4× the bandwidth in an equivalently-sized device compared to a prior generation, with the latest generation of PCIe, 800-GbE, 1.6-TbE Ethernet, and UCIe capabilities that we plan to use for next-generation data converters," Joshi said.
Device connectivity includes configurable transceivers at speeds up to 256 Gbits/s; hardened IP for 800-GbE and 1.6-TbE Ethernet; PCIe 6.0 and 7.0; plus DDR5, LPDDR5X, and LPDDR6 memory interfaces; MIPI, C-PHY 2.1, and D-PHY 3.0 support; and UCIe connectivity to enable future chiplets such as data converters and other technologies.
Security is another key foundational feature of the Agilex 27 as well as the Agilex 2X portfolio.
Altera's Secure Device Manager establishes a hardware root of trust for Agilex 27 FPGAs, with secure boot, identity, attestation, protected key management, and physical anti-tamper protection.
It also introduces full data-path encryption across key interfaces, including Ethernet MACsec, PCIe IDE, and Memory IME, and support for post-quantum cryptography. This allows customers to implement encryption using hardened IP, consuming less soft logic in the FPGA fabric.
The Agilex 25 FPGAs also deliver a high-performance fabric and embedded compute but with optimized I/O, transceivers, and peripherals for applications like 4K/8K video processing, drones and low-latency sensors.
The mid-range product family, optimized for I/O and transceiver mix, targets applications that need a high-performance fabric and also a greater emphasis on embedded compute, but don't need the highest levels of bandwidth, Joshi said.
The value-optimized products are the Agilex 23 and Agilex 22 FPGAs. The Agilex 23 FPGAs integrate embedded compute, real-time processing and functional safety, targeting robotics, industrial automation, and automotive systems. The Agilex 22 FPGAs are described as right-sized for I/O-centric systems, with high I/O density for board and rack control, motor control, root-of-trust and interface-bridging applications.
The value-optimized FPGAs target applications that don't need the highest levels of performance but still need the programmability, determinism, or the I/O capabilities that FPGAs provide, Joshi said.
Engineering samples for Agilex 27 FPGAs is expected in the second half of 2027. Quartus Prime software support for Agilex 27 FPGAs is available now in the Quartus Prime version 26.3. QuartusIQ is also available for download now as part of Quartus Prime Pro Edition 26.3.
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