How to Tackle Hidden Production Risks in Semiconductor Operations

By CRAIG WALTERS, Vice President, Business Process Outsourcing, Semiconductor, Kelly

Fabs apply enormous engineering discipline to their tools and recipes, but manual operations such as wafer lot packaging, reticle transport, preventive maintenance and parts cleaning get far less structured scrutiny, even though valuable material passes through human hands hundreds of times a day. Craig Walters of Kelly calls this the risk that hides in plain sight on the fab floor.

His answer is failure mode and effects analysis (FMEA), applied proactively by the business process outsourcing partners who run many of these operations. In one assessment of a manual wafer lot packaging area, Kelly’s team scored each step for severity and probability with the customer’s engineers, then introduced a more efficient bagging solution, ergonomic changes, structured technician rotation and updated checklists. A rescore showed a material reduction in high-risk steps.

Walters describes how the practice scales across sites, ties into 8D incident reviews and recognizes technicians who halt an operation when a risk warrants it. As CHIPS Act investment drives new capacity, he argues, supplying qualified technicians is the baseline, and the real value of a BPO partner lies in characterizing and reducing operational risk.

Click here to read the full article in Semiconductor Digest magazine.

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