From Wafers to Panels: Overcoming Lithography Challenges in Advanced Packaging

By STÉPHANE PELLEGRINI, Product Manager, ETEL and SHAHBAZ SOHRAB, Business Development Specialist – Semiconductor, HEIDENHAIN

AI-driven custom silicon is pushing advanced packaging toward high-density RDLs, TSVs and fine-pitch fan-out interconnects. Unlike front-end lithography, packaging lithography typically works at feature sizes around 1 µm, so overlay accuracy, throughput and thermal stability matter more than ever-smaller CDs, and those demands grow as substrates move from 300mm wafers to panels as large as 600 x 600mm.

Stéphane Pellegrini of ETEL and Shahbaz Sohrab of HEIDENHAIN examine what motion stages must deliver. With overlay requirements often below 100nm, a representative air-bearing stage held horizontal straightness within ±150nm and vertical straightness within ±120nm at scan speeds up to 1,000 mm/s over 300mm of travel. Speed stability during scanning and fast move-and-settle performance are just as important to throughput.

Thermal stability is the other key factor. Heat from linear motors and process temperature swings can cause overlay drift, so the authors describe water-cooled glider interfaces and magnetic paths, along with encoder scales mounted on thermally decoupled structures, to keep the metrology loop isolated from drift during long production runs.

Click here to read the full article in Semiconductor Digest magazine.

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