Simulation-Driven Thermal Modeling for SiC and GaN Converters

Silicon carbide (SiC) and gallium nitride (GaN) devices have solved the “switching loss” dilemma that limited the usage of silicon-based power devices in power electronics. Wide-bandgap (WBG) devices switch faster, offer higher breakdown voltages, and conduct with lower on-resistance per unit area.

However, to turn SiC and GaN’s outstanding figures of merit into a reliable commercial device, we have to find appropriate ways to get the heat out, considering it is concentrated in a very small area. This is particularly relevant for power converters, where, to achieve higher power densities, the die size can be significantly shrunk while maintaining the same voltage and current ratings as a conventional silicon chip.

At the die level, WBG power devices experience local heat fluxes and thermal power densities that can easily reach several kilowatts per square centimeter. If this heat is not managed appropriately, localized temperature spikes in small areas can cause thermal runaway, degrade gate oxide layers, crack solder joints due to mechanical stress, and lead to catastrophic device failure.

A recent review published in the MDPI journal Electronics highlighted that the performance of WBG is mainly constrained by the position of heat generation within the device and the effectiveness of heat dissipation from the package, rather than just the electrical characteristics of the semiconductor itself.

This is why simulation has become the primary design tool for thermal management in SiC and GaN converters, rather than a test procedure conducted late in a hardware program. Building and testing physical prototypes for every combination of die layout, packaging material, and cooling architecture is too slow and too expensive. Conversely, simulation lets engineers explore that design space computationally before committing to silicon (or, more precisely, to SiC or GaN).

SiC and GaN thermal physics

To develop accurate thermal models, we must first comprehend the main physical differences between SiC and GaN devices.

SiC power devices, such as SiC MOSFETs, are mainly used in high-voltage and high-power applications. SiC features a vertical device architecture. This means current flows vertically from the top surface through the bulk SiC substrate to the drain contact on the back of the chip. Heat generated in the active drift region travels downward through the chip, through a die-attach solder or silver-sinter layer, into a ceramic insulated substrate, and finally into a baseplate and heatsink.

4H-SiC has high thermal conductivity at room temperature, 3× that of silicon (about 490 W/m·K, compared with 150 W/m·K). However, under operation, the device is heated up, and its thermal conductivity decreases significantly according to a nonlinear law (Figure 1). This temperature dependence of degradation must be incorporated into the thermal models for SiC; otherwise, operation at high temperature will be dangerously underestimated.

GaN devices, such as GaN HEMTs, are prevalently used in high-frequency, lower- to medium-voltage applications. Most commercial power GaN devices have a lateral structure grown on silicon or SiC substrates. The current flows horizontally through a thin, two-dimensional electron gas (2DEG) channel, which is located below the top surface. The heat is then concentrated in a microscopic region near the gate edge. Because heat is generated in a small volume, lateral GaN devices can develop local hot spots, as shown in Figure 2.

The heat passes through several thin crystal transition layers before reaching the substrate. These different layers of materials form thermal barriers that resist the flow of heat. Therefore, GaN thermal modeling needs high spatial resolution in the gate-drain region to reproduce these localized peak junction temperatures.

The simulation toolchain

Simulation-driven thermal design for power converters is typically articulated on three connected levels.

3D simulation at the device and package level

Here, finite element analysis (FEA) and computational fluid dynamics (CFD) tools, such as Ansys Icepak and Siemens Simcenter Flotherm, are used to determine the heat conduction and convection physics that occur inside a module. This includes the die attach, substrate, baseplate, and cooling channel.

3D FEA is useful for evaluating real-world physical defects and structural limits. These include solder voiding analysis (air voids, or bubbles, created inside the solder or sintering layers beneath the chip), substrate heat spreading (heat does not travel straight down; rather, it spreads outward at an angle through the package layers), and thermomechanical stress (such as thermal expansion mismatches).

For high-power converters, heat has to be eventually dissipated from the heatsink to the ambient air or a liquid coolant. CFD models can simulate fluid flow and solid heat conduction. This helps engineers design appropriate cooling solutions such as direct-to-chip liquid cold plates and air-cooled heatsinks.

In SiC power modules, flat copper baseplates are often replaced by integrated pin-fin structures directly immersed in liquid coolant. CFD simulations are used to optimize the pin shape, fluid velocity, and pressure drop for maximum heat extraction. For GaN-based power supplies, CFD is used to optimize heatsink fin spacing, orientation, and fan placement to remove stagnant air pockets and achieve uniform cooling.

These models are physically very accurate but computationally expensive (they involve partial differential equations). The execution of a 3D thermal simulation can take hours or even days. This makes them impractical for circuit simulators, which must calculate plenty of high-speed electrical switching events per second.

Reduced-order thermal models

A way to overcome the computational effort involved with 3D FEA is to extract simplified Cauer or Foster compact lumped-parameter RC network models, or more general reduced-order models (ROMs), from the detailed 3D simulation. These compact models reproduce the transient thermal response of the full model to acceptable accuracy while running orders of magnitude faster.

Figure 3 is a Cauer network with thermal resistors and capacitors connected in a ladder-like arrangement, with all capacitors connected to ground (ambient or case temperature). Instead, a Foster network consists of parallel resistor-capacitor pairs connected in series (see Figure 4).

ROMs allow engineers to couple thermal behavior with circuit-level switching simulation over many cycles. In fact, they enable simultaneous electrical and thermal simulation (e.g., in SPICE, PLECS, or MATLAB/Simulink).

These thermal models are based on the mathematical analogy between heat transfer and the flow of electrical current. Temperature maps to voltage (V), thermal power (heat) maps to current (A), thermal resistance maps to electrical resistance (Ω or K/W), and thermal capacitance maps to electrical capacitance (F or J/K).

Siemens further expanded this concept with its Embeddable Boundary-Condition-Independent ROM (BCI-ROM) technology, available in Simcenter Flotherm. This approach lets a semiconductor supplier share an accurate thermal model of a packaged device with a downstream customer’s 3D thermal design flow without revealing insights on the internal physical construction of the die and package. According to Siemens, this is the first time that data can be shared while protecting OEMs’ IP.

Figure 5 shows how this approach works. On the top left is a full 3D board-level thermal contour, whereas on the bottom left, a multi-die IC package model is extracted into a lightweight, IP-protected Embeddable BCI-ROM format (middle). The transient temperature response over a 60-second power cycle is shown on the top right, comparing 3D models (FCBGA J1 and U3) against their respective Embeddable BCI-ROMs (dashed lines). These graphs demonstrate near-identical accuracy over different power levels. Finally, the image on the bottom right shows the integration of the BCI-ROM into a board-level CFD airflow simulation.

System-level electrothermal co-simulation

At the top level, thermal networks are coupled with circuit simulators, typically MATLAB/Simulink, PLECS, PSIM, or similar ones, so that conduction and switching losses computed from the electrical simulation feed junction temperature predictions, and temperature-dependent device parameters (on-resistance, threshold voltage, leakage) feed back into the electrical model.

This closed-loop, electrothermal approach is now standard practice for evaluating converter efficiency, dynamic response, and thermal margin together rather than in isolation, and it is the methodology used in recent comparative studies of SiC and GaN traction inverters and DC/DC converters for electric-vehicle applications. Static thermal modeling ignores this loop, leading to dangerously optimistic efficiency and temperature predictions.

Industry use cases and next steps

Onsemi, working with Ansys, developed a multifidelity thermal modeling process to validate SiC MOSFET power modules used in industrial applications. The workflow chains Ansys SpaceClaim for 3D solid-model generation, Ansys Icepak for thermal impedance simulation, and downstream electrical and mechanical analysis into a single automated, web-based platform. This approach reduces what was previously a manual, multi-tool process into something that can be run routinely as part of module qualification, improving accuracy in the process.

In SiC-based power electronic converters, traditional numerical simulations are difficult, as the fast switching behavior and dynamic load profiles require many calculation steps. Fast and accurate temperature estimation using advanced machine-learning (ML) techniques is being introduced. ML architectures are trained on dataset combinations generated from calibrated FEA thermal simulations and empirical sensor measurements.

These ML algorithms create a nonlinear mapping between the observable operational metrics (such as load current, ambient temperature, switching frequency, duty cycle, heatsink coolant flow) and the instantaneous device junction temperatures.

Once trained, these surrogate models run in milliseconds or microseconds, providing multi-point junction temperature predictions with negligible computational overhead.

Thermal modeling also plays a significant role in operational lifetime estimation and physics-of-failure reliability engineering for power MOSFETs and WBG modules. The repeated thermal expansion and contraction cycles resulting from dynamic power variations induce significant thermo-mechanical stress at material interfaces with mismatched coefficients of thermal expansion.

When electricity flows through a chip, it heats up and expands; when it then cools, it shrinks. Because the chip is made of different layers (silicon, solder, copper wires), these layers expand at different rates. After many operating hours, this phenomenon can cause bond-wire liftoff (see Figure 6), die-attach cracking, and structural degradation.

To predict when these failures will happen without waiting years for physical testing, simulation-driven lifetime estimation techniques are used. These include: dynamic profiles, rainflow-counting algorithms, and lifetime models based on cycle amplitudes and mean junction temperatures.

Cover image: Adobe Stock

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