Blog Review: Oct. 7

Siemens’ Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala explore how CFETs and buried power rails come together to reduce the chip area needed, improve power efficiency, and help meet the high-performance needs of AI accelerators, data centers and mobile processors.

Synopsys’ Thomas Andersen says the strongest results come when agentic AI can leverage the company-specific knowledge that makes each engineering organization distinct, such as its methodologies, design history, priorities, best practices, and accumulated experience.

Cadence’s Reela Samuel considers what separates agentic AI from traditional and AI-assisted EDA workflows, noting that while individual operations in the loop are not necessarily new, what changes is how those operations can be coordinated.

Keysight’s Stephen Douglas urges the industry to start rapid prototyping of the hardest 6G architectural questions as the window narrows to turn promising concepts into mature standards, interoperable products, and deployable systems.

Arm’s Francisco Socal introduces AMBA C2C, which extends chiplet connectivity across AXI and CHI with scalable protocol subsets, interoperability, and flexible transport support for fully coherent, advanced heterogeneous compute.

SEMI’s Saifi Usmani highlights finalists in the Startups for Sustainable Semiconductors program, which offer solutions from monolithic integrated voltage regulators to wafer defect inspection and characterization to a GPU-native physics simulation platform.

Plus, check out the blogs featured in the latest Automotive, Security & AI newsletter:

Infineon’s Karthik Rangarajan shows how distributed NVM supports high-endurance telemetry logging, functional safety, and time-sensitive networking where resilience is critical.

Rambus’ Vincent van der Leest demonstrates how roots of trust are beginning to assume a broader role as platform security orchestrators.

Cadence’s Kartik Hegde looks beyond RTL to a new representation that allows engineers to express intent more intuitively.

Synopsys’ Brian Davenport outlines a development flow to ensure that hardware can do its job in the field without being vulnerable to attacks or leakage of private data.

Siemens EDA’s Kartik Sahajpal and Prashant Dixit dig into integration and verification challenges in PCIe-over-UCIe systems, including how link-state transitions affect transaction behavior.

Imagination’s Alex Pim examines time to first token and inter-token latency, and how they apply to the two main stages of LLM compute — prefill and decode.

Keysight’s Marc Witteman contends that compliance with trade restrictions is no longer about proving where a device was built, but about how the product works.

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