Why Your Crystal Oscillator Won't Start: Load Capacitance and Startup Margins

The Symptom: Works on the Bench, Dies in Production

The classic failure: the RTC keeps time in the lab, but a percentage of production boards have dead clocks — or clocks that run fast, or start only when you touch the crystal with a finger. We've seen all three from the same batch. This is almost never the crystal being "broken." It is a Pierce oscillator running out of startup margin, and the three usual culprits are load capacitance mismatch, ESR that exceeds what the oscillator's negative resistance can overcome, and drive level problems. Here is how to check each one.

How a Pierce Oscillator Actually Starts

The oscillator IC's amplifier must overcome the crystal's equivalent series resistance (ESR) every cycle. The amount of "negative resistance" (Rneg) the amplifier provides depends on the IC's gain, the load capacitors, and the PCB parasitics. The industry rule of thumb is a safety factor of 3–5×: Rneg should be at least 3–5 times the crystal's ESR for reliable startup over temperature and aging. We treat that as a floor, not a target.

You can measure Rneg directly: insert a resistor in series with the crystal and increase it until oscillation stops. The critical value plus the crystal ESR is your Rneg. If you get less than 3× ESR — especially at the cold end of the temperature range, where ESR rises — you have found the production failure.

For 32.768 kHz watch crystals, typical ESR is 35–90 kΩ. RTC oscillator circuits in microcontrollers are designed around that, but a crystal at the high end of the ESR spec, on a board with extra stray capacitance, can land exactly on the wrong side of the margin.

Load Capacitance: Two Caps, One Formula

The crystal's datasheet specifies a load capacitance (CL) — typically 12.5 pF for 32.768 kHz watch crystals, sometimes 9, 6, or 4 pF. The oscillator must present exactly that capacitance to the crystal, from the two load caps plus every stray pF on the PCB:

CL = (C1 × C2) / (C1 + C2) + Cstray

With equal caps, this simplifies to C1 = C2 = 2 × (CL − Cstray). Worked example: a 12.5 pF crystal with 2–4 pF of stray capacitance (pads, vias, oscillator pin) needs C1 = C2 ≈ 18–22 pF. Use 18 pF or 22 pF standard values and you are inside the spec.

Get this wrong and the clock still starts — but it is off frequency. Crystal pullability follows S = C1/(2(C0 + CL)²), which for a typical watch crystal (motional capacitance ~3 fF, shunt capacitance ~1.5–2 pF) lands around 5–8 ppm per pF of load error. A 12.5 pF crystal forced to operate at 20 pF equivalent shifts tens of ppm — an RTC that gains or loses seconds per day. That "fast clock" field report is usually a capacitor value, not a crystal defect. When we get a fast clock back for analysis, the two caps get measured first.

Startup Time and Drive Level

Startup is exponential, with a time constant on the order of τ ≈ Q/(π·f·(N−1)), where N is the Rneg/ESR margin ratio. Watch crystals have Q of roughly 40,000–70,000, which puts normal startup in the 0.1–1 s range — and pushes it dramatically longer as N approaches 1. If your firmware assumes the RTC is valid 10 ms after power-up, you are part of the problem. That one is easy to fix.

Drive level is the other silent killer. Watch crystals are typically rated for a maximum drive of 0.1–1 µW; overdrive (too-small load caps, overly strong amplifier gain) causes frequency drift, faster aging, and eventually failure to start. Measure it with a low-capacitance or active probe — a 10 pF scope probe on a high-impedance 32 kHz node is itself enough to change the answer.

The Debug Checklist

Verify the crystal's ESR against the oscillator IC's specified maximum (MCU datasheets usually state a max ESR for the LSE).
Recompute C1 = C2 = 2 × (CL − Cstray), including pad, via, and pin capacitance — then check what value is actually on the BOM.
Measure Rneg ≥ 3× ESR, at the cold corner.
Check drive level with a 1 pF-class probe; verify it is below the crystal's max.
Look for flux or solder residue on the 32 kHz pads — a high-impedance node, and contamination is enough to stop it.
If the margin is thin: choose a lower-ESR crystal, use the MCU's internal programmable load caps (many microcontrollers offer selectable LSE capacitance), or move to a temperature-compensated oscillator module.

Start with step 2 — the cheapest fix on the list.

Source Crystals With the Specs You Need

Every one of these checks starts with a datasheet that states ESR, CL, and drive level. When we order these, that's the first page we turn to. Search parts for 32.768 kHz and MHz crystals with documented CL and ESR specs, and verify availability before you freeze the layout — on partscubeglobal.com, the crystal that meets your margin analysis is the one you can actually buy.